Power11
| Power11 | |
|---|---|
| Designer | IBM |
| Manufacturer | Samsung Foundry |
| Announced | July 8, 2025 |
| Production availability | July 25, 2025 |
| Power ISA | 3.1 |
| Architecture | 64-bit, bi-endian |
| Process node | Samsung enhanced 7 nm with EUV lithography |
| Die size | 654 mm² |
| Transistors | 30 billion |
| Packaging | Advanced 2.5D package with Samsung silicon interposer |
| Power delivery | Integrated Stacked Capacitor (ISC) |
| Maximum cores | 16 per die |
| Multithreading | Up to SMT8 |
| Clock range | Approximately 3.8–4.4 GHz |
| L1 cache / core | 96 KiB instruction, 64 KiB data |
| L2 cache / core | 2 MiB |
| L3 cache / die | Up to 128 MiB |
| Memory attachment | OMI (DDR5; selected DDR4 carry-over configurations) |
| I/O | PCI Express 5.0 |
| Modules | SCM, eSCM, DCM |
| PVR family | 0x0082[1] |
| Publicly modelled stepping | DD2.0 (PVR 0x00821200)[2] |
| Blob-free operation | No known fully blob-free shipping configuration |
| ← Power10 | |
Power11 is IBM's processor generation for enterprise Power systems introduced in 2025. It succeeds POWER10, implements version 3.1 of the Power ISA, and is used in IBM scale-up, scale-out, Linux-oriented and cloud systems. IBM announced Power11 and its first systems on July 8, 2025, with general availability beginning on July 25, 2025.[3]
Power11 is manufactured by Samsung on a enhanced 7 nm process. A processor die contains up to 16 cores, each capable of eight simultaneous hardware threads. Depending on the processor module and server model, operating frequencies range from approximately 3.8 GHz to 4.4 GHz.[4]
Power11 implements the same Power ISA revision as Power10. Its principal changes are therefore microarchitectural and platform-level: a revised core, fully enabled 16-core configurations, enlarged L1 caches, higher aggregate cache capacity, increased memory bandwidth, advanced 2.5D packaging, and expanded reliability, availability and serviceability features.
Contents
History
IBM introduced Power11 on July 8, 2025. The initial product line consisted of the scale-up Power E1180 and Power E1150, the scale-out Power S1124 and Power S1122, and the Linux-oriented Power L1124 and Power L1122. Power11 instances were also announced for IBM Power Virtual Server.[3]
IBM presented additional Power11 processor-architecture details at Hot Chips 2025.[5]
On July 15, 2026, IBM announced the Power S1112, a compact single-socket entry and edge system. IBM scheduled general availability for July 24, 2026.[6][7]
Architecture
Process and packaging
Power11 continues to use a Samsung 7 nm process rather than moving to a smaller nominal process node. IBM describes the implementation as a refined or newer iteration of Samsung's 7 nm technology.[5][8]
The processor uses an advanced 2.5D stacked package. IBM's Hot Chips presentation, as reported by ServeTheHome, identifies a Samsung-fabricated silicon interposer as the basis of this package design.[5] The silicon interposer provides high-density package-level connectivity and is distinct from the processor dies mounted on it.
Power11 also introduces an Integrated Stacked Capacitor (ISC) as a package-level power-delivery feature. IBM presents the ISC and advanced 2.5D packaging as related package innovations, but they are not the same component: the silicon interposer provides interconnect, while the ISC supplies local decoupling capacitance to improve power-delivery stability.[9]
IBM lists a Power11 die size of approximately 654 mm² and approximately 30 billion transistors or devices. IBM notes in its comparison material that its counting methodology changed, so the figure is not directly comparable with the previously published figure of 18 billion transistors for Power10.[10]
Cores and cache
A Power11 die contains up to 16 cores. Power10 product configurations exposed a maximum of 15 active cores per die, while Power11 supports configurations in which all 16 cores are active. A fully enabled die therefore provides up to 128 hardware threads and 128 MiB of L3 cache.[10]
Each Power11 core contains:
- 96 KiB of L1 instruction cache;
- 64 KiB of L1 data cache;
- 2 MiB of private L2 cache; and
- an associated 8 MiB portion of the on-die SRAM L3 cache.[10]
A fully enabled die consequently contains an aggregate 160 MiB of L2 and L3 cache: 32 MiB of private L2 cache and 128 MiB of L3 cache. This figure does not include the L1 caches.
Each core retains four Matrix Math Accelerator (MMA) engines. The Power11 implementation adds improvements to the MMA and SIMD facilities and supports matrix operations using FP64, FP32, FP16, bfloat16 and INT8 data formats.[4]
Power11 systems provide an Energy Efficient Mode that reduces operating voltage and frequency. IBM reports up to 28% better energy efficiency in this mode compared with Power11 Maximum Performance Mode, based on IBM internal measurements across selected system configurations.[4]
Memory subsystem
Power11 attaches memory through the OpenCAPI Memory Interface (OMI), continuing the architecture introduced with Power10. Main memory is not connected to an integrated conventional DDR controller on the processor die; OMI links connect the processor module to buffered memory modules containing an OMI-to-DDR bridge.[10]
New Power11 configurations use DDR5 memory. Selected enterprise configurations can reuse compatible OMI-attached DDR4 memory from Power10 systems.[4]
IBM cites peak memory bandwidth of up to 512 GB/s per socket for Power11, compared with up to 409 GB/s for Power10. The exact capacity and bandwidth depend on the processor module, server model and installed memory configuration.[4]
The mandatory use of OMI is relevant to firmware ownership and auditability; see Owner control and firmware.
I/O
Power11 provides PCI Express 5.0 connectivity for storage, networking and accelerator devices. Supported slot counts and expansion drawers vary by server model. PCIe Gen3 expansion drawers used with some earlier IBM Power systems are not supported by the Power11 scale-out family.[10]
Accelerators
The IBM Spyre Accelerator is an optional external AI accelerator connected through PCI Express. It is not part of the Power11 processor die. Spyre adds accelerator memory and support for additional low-precision AI data formats, including FP8 and FP16.[11]
Most supported Power11 systems can attach up to eight Spyre adapters through one accelerator expansion drawer. The Power E1180 supports one or two drawers and therefore up to sixteen Spyre adapters.[11]
Processor modules
- Single-chip module (SCM)
- One Power11 processor die. Depending on the product configuration, an SCM provides up to 16 active cores. Most SCM configurations reserve one additional physical core as a spare; fully enabled 16-core configurations do not.
- Entry single-chip module (eSCM)
- A low-core-count module physically derived from the two-die design. Processor cores are enabled on one die, while the second die supplies additional I/O and PCIe-switching functions. Power11 eSCMs are offered with four or ten active cores and do not include a spare core.[10]
- Dual-chip module (DCM)
- Two Power11 dies in one processor module. DCM configurations provide up to 30 active cores and normally reserve two additional physical cores as spares.[10]
Spare cores allow the platform firmware and hypervisor to move work away from a core identified as failing. The feature is part of the complete system RAS implementation rather than a user-selectable additional processor resource.
Reliability, availability and serviceability
Power11 systems continue IBM's reliability, availability and serviceability approach. Depending on the server model and software configuration, supported functions include:
- processor-core sparing and dynamic failover;
- memory error detection and correction;
- redundant service processors and selected redundant system components;
- concurrent or live firmware maintenance;
- Live Partition Mobility under PowerVM;
- predictive failure analysis; and
- automated diagnostic and service-data collection.
IBM estimates that the Power E1180 can achieve 99.9999% stand-alone availability, corresponding statistically to approximately 31.5 seconds of unplanned downtime per year. This is a system-level availability estimate, not a guarantee for every Power11 processor or server configuration.[12]
IBM also markets Power11 around a goal of zero planned downtime for maintenance. Achieving this goal depends on the complete hardware and software stack, including redundancy, PowerVM, management infrastructure, operating-system support and suitable operational procedures.[13]
Security
Power11 systems provide always-on main-memory encryption, secure boot, firmware-integrity verification and protected virtualization. IBM also adds quantum-safe cryptographic capabilities to parts of the platform security and management stack, including selected secure-boot, key-management and partition-mobility operations.[14]
These functions depend on IBM-supplied processor firmware, service-processor firmware, PowerVM and supported operating systems. Secure boot verifies an IBM-authorized software chain; it does not by itself make every component owner-inspectable or owner-replaceable.
Owner control and firmware
Power11 retains OMI as its mandatory memory-attachment architecture. No shipping Power11 system is currently known to provide a fully owner-controlled, blob-free firmware stack. The firmware and owner-control issues first documented for POWER10 are therefore expected to remain relevant.See POWER10: Owner control and firmware for background.
Comparison with Power10
The values below are processor-generation maxima. They are not necessarily available simultaneously in one system configuration.
| Characteristic | Power10 | Power11 |
|---|---|---|
| Process | Samsung 7 nm with EUV lithography | Samsung enhanced 7 nm with EUV lithography[5] |
| Processor packaging | SCM and DCM | SCM, eSCM and DCM; advanced 2.5D package with silicon interposer[5] |
| Maximum active cores per die | 15 | 16[10] |
| Maximum hardware threads per die | 120 | 128 |
| Maximum clock frequency | Approximately 4.0–4.15 GHz | Up to approximately 4.4 GHz[4] |
| L1 instruction cache | 96 KiB per core | 96 KiB per core[10] |
| L1 data cache | 64 KiB per core | 64 KiB per core[10] |
| L2 cache | 2 MiB per core | 2 MiB per core[10] |
| Maximum L3 cache per die | 120 MiB | 128 MiB[10] |
| Peak memory bandwidth | Up to 409 GB/s | Up to 512 GB/s[4] |
| Memory attachment | OMI | OMI[10] |
| PCI Express | 5.0 | 5.0[10] |
| Power ISA version | 3.1 | 3.1 |
| Matrix acceleration | Four MMA engines per core | Four enhanced MMA engines per core[4] |
| Known fully blob-free shipping configuration | No | No |
Systems
As of July 2026, shipping and announced Power11 systems are supplied by IBM.
| System | Class | Maximum configured cores | Notes |
|---|---|---|---|
| Power E1180 | Enterprise scale-up | 256 | Up to 16 sockets and up to 64 TB of DDR5 memory.[15] |
| Power E1150 | Enterprise midrange | 120 | Four sockets and up to 16 TB of memory.[16] |
| Power S1124 | Scale-out, 4U | 60 | One- or two-socket scale-out system.[10] |
| Power S1122 | Scale-out, 2U | 60 | One- or two-socket system with up to 4 TB of memory.[10] |
| Power L1124 | Linux scale-out, 4U | 60 | Linux-oriented counterpart to the Power S1124.[10] |
| Power L1122 | Linux scale-out, 2U | 60 | Linux-oriented counterpart to the Power S1122.[10] |
| Power S1112 | Entry and edge | 10 | Single-socket half-width rack or tower system with up to 512 GB of DDR5 memory. General availability was scheduled for July 24, 2026.[7][6] |
| IBM Power Virtual Server | Cloud | Varies | Power11-based logical partitions supplied through IBM's Power Virtual Server service.[3] |
Operating systems and virtualization
Power11 systems support AIX, IBM i and selected Linux distributions. Current supported Linux distributions use the 64-bit little-endian ppc64le architecture.
PowerVM is IBM's principal production virtualization environment for Power11 systems. It provides logical partitioning, virtual I/O, shared processor and memory pools, dynamic resource allocation and Live Partition Mobility.
Initial upstream Linux recognition of Power11 architected and raw PVR values entered the Linux 6.9 development cycle.[17] QEMU also implements a powernv11 machine that emulates a PowerNV system at the skiboot firmware interface.[18] .
References
- ↑ PowerPC processor-version definitions, Linux kernel source.
- ↑ PowerPC CPU model definitions, QEMU source.
- ↑ 3.0 3.1 3.2 IBM Power11 Raises the Bar for Enterprise IT, IBM Newsroom, July 8, 2025.
- ↑ 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Implementing AI on Power11: Introducing the IBM Spyre Accelerator, IBM Redbooks, SG24-8592, 2026.
- ↑ 5.0 5.1 5.2 5.3 5.4 Patrick Kennedy, IBM's Power11 Processor Architecture at Hot Chips 2025, ServeTheHome, August 2025.
- ↑ 6.0 6.1 IBM Launches New Power Systems and Software Built for Enterprises, IBM Newsroom, July 15, 2026.
- ↑ 7.0 7.1 IBM Power S1112, IBM.
- ↑ IBM Power Processor, This One Goes to 11, Semiconductor Engineering, September 2025.
- ↑ W. Todd Boyd, Introducing IBM Power11 — Power Systems Overview, IBM, July 2025.
- ↑ 10.00 10.01 10.02 10.03 10.04 10.05 10.06 10.07 10.08 10.09 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 IBM Power11 Scale-Out Servers: Introduction and Overview, IBM Redbooks, SG24-8590, 2025.
- ↑ 11.0 11.1 IBM Spyre Accelerator on IBM Power, IBM Documentation, 2026.
- ↑ IBM Power E1180: Introduction and Overview, IBM Redbooks, SG24-8587, 2025.
- ↑ Zero Downtime, Automation, and Energy Optimization on IBM Power11, IBM Redbooks, SG24-8596, 2026.
- ↑ Security and Cyber Resilience with IBM Power11, IBM Redbooks, SG24-8595, 2026.
- ↑ IBM Power E1180, IBM.
- ↑ IBM Power E1150, IBM.
- ↑ Initial IBM Power11 Enablement Begins With Linux 6.9, Phoronix, March 2024.
- ↑ PowerNV family boards (powernv8, powernv9, powernv10, powernv11), QEMU documentation.
