POWER10

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Processor Information
Power10
Designer IBM
Manufacturer Samsung Foundry
Announced August 17, 2020
Production availability September 2021
Power ISA 3.1
Architecture 64-bit, bi-endian
Process node Samsung 7 nm FinFET with EUV lithography
Die size 602 mm²
Transistors 18 billion
Packaging Organic substrate
Power delivery Conventional package decoupling
Maximum cores 15 SMT8 cores per die
Multithreading Up to SMT8
Clock range Approximately 2.45–4.15 GHz
L1 cache / core 96 KiB instruction, 64 KiB data
L2 cache / core 2 MiB
L3 cache / die Up to 120 MiB
Memory attachment OMI (DDR4 and DDR5)
I/O and interconnect PCI Express 5.0, PowerAXON
Modules SCM, eSCM, DCM
PVR family 0x0080[1]
Publicly modelled stepping DD2.0 (PVR 0x00801200)[2]
Blob-free operation No known fully blob-free shipping configuration
← POWER9 Power11 →

Power10 (introduced as POWER10) is IBM's processor generation for enterprise Power systems introduced in 2020 and first shipped in systems in 2021. It succeeds POWER9, implements version 3.1 of the Power ISA, and is used in IBM enterprise, midrange, scale-out, Linux-oriented and cloud systems.[3][4]

Power10 is manufactured by Samsung on a 7 nm EUV process. A processor die measures approximately 602 mm², contains approximately 18 billion transistors, and provides up to 15 active SMT8 cores. Depending on the processor module and server model, marketed operating-frequency ranges extend from approximately 2.45 GHz to 4.15 GHz.[5][6][7]

The generation introduced a substantially revised core, the Matrix Math Accelerator (MMA), OpenCAPI Memory Interface (OMI) attachment for main memory, PowerAXON high-speed links, PCI Express 5.0, transparent main-memory encryption and a new packaging family consisting of single-chip, entry single-chip and dual-chip modules.

History

IBM announced POWER10 on August 17, 2020, in conjunction with the Hot Chips 32 conference. IBM stated that the processor would be manufactured by Samsung using a 7 nm process and positioned it as the successor to POWER9 for enterprise systems.[3][5]

On September 8, 2021, IBM announced the Power E1080, the first production server based on Power10. The scale-up E1080 supports up to 16 processor sockets, 240 active cores and 64 TB of memory.[4][8]

IBM expanded the Power10 family in July 2022 with the four-socket Power E1050 and the Power S1014, S1022s, S1022 and S1024 scale-out systems. Linux-oriented L1022 and L1024 variants were also introduced.[9][6][7]

In May 2024, IBM announced the Power S1012, a compact single-socket entry and edge system. General availability began on June 14, 2024. The S1012 is available as a half-width 2U rack system or a tower and supports one, four or eight active Power10 cores.[10][11]

Architecture

Process and die

Power10 is fabricated by Samsung using a 7 nm EUV process with 18 metal layers. IBM gives a die area of approximately 602 mm² and a transistor count of approximately 18 billion.[5][8]

The die contains up to 15 active SMT8 cores, eight memory-controller-unit channels for OMI attachment, PCI Express 5.0 controllers and PowerAXON links. IBM's initial Hot Chips presentation described both one-die single-chip modules and two-die dual-chip modules.[5]

IBM's Hot Chips material also described a two-die socket as providing up to 30 SMT8 cores or 60 SMT4 core equivalents. The latter description reflects the two execution-resource domains within each SMT8 core. IBM's production-system documentation and licensing count physical processor capacity in SMT8 cores; marketed Power10 systems do not list a separate 30-core-per-die product.[5][6]

Cores and cache

Each Power10 core supports up to eight simultaneous hardware threads. The core is divided into two largely symmetric execution-resource domains; IBM architecture diagrams describe one half of the core as an SMT4-core equivalent.[5][6]

A Power10 SMT8 core contains:

  • two 48 KiB L1 instruction-cache structures, for 96 KiB in total;
  • two 32 KiB L1 data-cache structures, for 64 KiB in total;
  • 2 MiB of private L2 cache; and
  • an associated 8 MiB region of the on-die SRAM L3 cache.[6][12]

All active cores on a die can access the complete non-uniform cache architecture (NUCA) L3 cache. A fully enabled 15-core die therefore provides up to 30 MiB of aggregate L2 cache and 120 MiB of L3 cache.[8]

Compared with the POWER9 SMT8 core, Power10 increases the L1 instruction cache from 64 KiB to 96 KiB, increases private L2 cache from 512 KiB to 2 MiB, widens execution resources and reduces several cache and translation latencies.[6][13]

Each core contains eight vector-scalar execution slices and four Matrix Math Accelerator units. The MMA facility implements the matrix instructions introduced with Power ISA 3.1 and is intended for matrix multiplication, convolution and other numerical kernels, including reduced-precision AI inference.[14][6]

Memory subsystem

Power10 uses the OpenCAPI Memory Interface (OMI) as its processor-side main-memory attachment. Main-memory DRAM is not directly driven by a conventional DDR interface on the processor die. Instead, high-speed serial OMI links connect the processor to buffer controllers that translate OMI transactions to DDR memory signaling.[8]

Most Power10 systems use OMI-attached Differential DIMMs (DDIMMs). Depending on system generation and configuration, these modules contain DDR4 or DDR5 memory. IBM documentation for updated S1022 and S1024 configurations lists peak bandwidth of up to 409 GB/s per socket with DDR4 and up to 819 GB/s per socket with DDR5. Actual capacity and bandwidth depend on the processor module, number of populated memory channels and server model.[7]

The Power S1012 is a special low-cost implementation. It retains OMI between the processor module and memory-controller devices, but the OMI-to-DDR controllers are soldered to the system planar and expose four industry-standard DDR4 RDIMM slots. The S1012 supports up to 256 GB and a peak memory bandwidth of 102 GB/s.[11]

The mandatory OMI architecture is relevant to firmware ownership and auditability; see Owner control and firmware.

I/O and interconnect

Power10 provides three principal classes of high-speed off-chip interface:

  • OMI links for buffered memory attachment;
  • PCI Express 5.0 for storage, networking and accelerator devices; and
  • PowerAXON links, which can be configured for processor-to-processor symmetric-multiprocessing connectivity and coherent accelerator or memory-fabric functions.[5][8]

The interfaces operate at signaling rates of up to 32 GT/s. A one-die module exposes fewer aggregate lanes than a two-die module; the exact number of usable PCIe lanes and slots depends on the server planar and processor configuration.[5][7]

PowerAXON also forms the architectural basis for IBM's Memory Inception technology, which allows memory in another Power10 system to be accessed through a coherent fabric. Availability depends on IBM system, firmware and software support and is not a generic capability of every Power10 machine.[3][8]

Accelerators and cryptography

Power10 integrates four MMA units per core for matrix and reduced-precision workloads. It also expands in-core cryptographic execution resources relative to POWER9 and supports hardware acceleration for algorithms including AES and SHA families.[5][15]

System software and operating-system libraries are required to make effective use of these facilities. The presence of MMA units does not make Power10 a replacement for all discrete GPU or accelerator workloads; it principally targets inference and numerical kernels close to operational data.

Processor modules

Single-chip module (SCM)
One Power10 die in the processor module, providing up to 15 active SMT8 cores and up to 120 hardware threads. The SCM is used by the Power E1080. IBM lists a frequency range of approximately 3.6–4.15 GHz for SCM configurations.[8][6]
Dual-chip module (DCM)
Two Power10 dies in one processor module. The architecture presentation showed a maximum of 30 SMT8 cores per DCM, but IBM's shipping DCM configurations expose up to 24 active SMT8 cores per socket. DCMs are used by the Power E1050 and by higher-core-count S1022, S1024, L1022, L1024 and S1014 configurations.[5][6][7]
Entry single-chip module (eSCM)
Despite its name, the Power10 eSCM is physically based on the two-die package. Active processor cores and memory resources are enabled on one die, while the second die contributes I/O and PCIe connectivity. Power10 eSCMs provide up to eight active SMT8 cores and are used by systems including the S1012, lower-core-count S1014 and S1022s.[6][11]

The distinction between architectural maxima and marketed configurations is important. A Power10 die contains resources for the architecture described at Hot Chips, while IBM enables different core counts, clock ranges, memory paths and I/O capabilities according to module and system model.

Reliability, availability and serviceability

Power10 systems continue IBM's reliability, availability and serviceability (RAS) architecture. Available functions vary by server model and configuration and can include:

  • error-correcting memory, memory scrubbing and fault isolation;
  • Active Memory Mirroring on supported models;
  • predictive failure analysis and dynamic deallocation of failing resources;
  • redundant power supplies, fans, service processors and other components on selected systems;
  • concurrent maintenance of selected storage, power and I/O components;
  • PowerVM Live Partition Mobility;
  • automated first-failure data capture, diagnostics and service-data collection; and
  • processor and memory recovery functions coordinated by platform firmware and the hypervisor.[8][7][16]

The availability level of a Power10 deployment is a property of the complete system and software configuration, not of the processor alone. Entry systems such as the S1012 intentionally omit some functions available in larger scale-out and enterprise machines.[11]

Security

Power10 introduced transparent main-memory encryption across the Power server family. IBM states that memory encryption is enabled in hardware without application changes or separate key-management setup. On supported systems it protects data transferred between processor and main memory and is enabled by default.[4][17]

The platform also supports secure-boot and firmware-integrity mechanisms, hardware-assisted partition isolation, cryptographic acceleration and protections against selected control-flow and side-channel attacks. The availability and exact implementation of these features depend on system firmware, PowerVM, management infrastructure and operating-system support.[17][5]

These security mechanisms should not be confused with owner control. Cryptographic verification can ensure that a component is authorized by IBM while still leaving that component closed to owner inspection or modification.

Owner control and firmware

Public reporting and statements attributed to Raptor Computing Systems identify two Power10-specific closed firmware areas:

  • firmware used by the off-chip OMI-to-DDR memory bridge, including firmware associated with the memory-controller and DDR-PHY implementation; and
  • firmware for an on-chip PPE I/O processor, distributed as compiled firmware without corresponding public source code.[18][19][20]

The second component is often summarized as a “PCIe blob”, but the publicly available material identifies it more precisely as firmware for the on-chip PPE I/O processor. Its complete responsibilities are not publicly documented, so it should not be described as only a PCIe firmware component.[19]

Raptor Computing Systems cited the closed firmware requirements as the reason it had no plan to develop a Power10 system. The same issue, together with pandemic disruption and the industry's move toward CXL, contributed to the decision not to manufacture the proposed Condor board.[21]

No shipping Power10 system is known to provide a fully owner-controlled, blob-free firmware stack comparable to Raptor's POWER9 systems. OMI is the processor-side memory architecture across the Power10 family, including the S1012 implementation with planar-mounted OMI-to-DDR controllers, so the memory path cannot be replaced by directly connecting ordinary DDR DIMMs to an integrated processor DDR controller.[11][21]

Open-source Power10 enablement nevertheless exists. Linux recognizes the Power10 processor-version family, QEMU provides a powernv10 machine and a power10_v2.0 CPU model, and skiboot provides the OPAL firmware interface used by the QEMU PowerNV model.[1][22][2]

QEMU explicitly models the system at the skiboot interface and does not emulate lower-level HostBoot responsibilities such as DRAM training. Emulation and operating-system support therefore do not demonstrate that a physical Power10 machine can be operated with a completely auditable owner-controlled firmware stack.[22]

Consequently, Raptor Computing Systems POWER9 platforms remain the most recent commercially available systems with a fully owner-controlled firmware stack.[18][21]

Comparison with POWER9

POWER9 was produced in distinct 12-core SMT8 and 24-core SMT4 designs. To avoid mixing unlike configurations, the core-count rows below compare the SMT8 enterprise implementations. Other values are processor-generation characteristics and can vary by product.

Characteristic POWER9 Power10
Process GlobalFoundries 14 nm FinFET[13] Samsung 7 nm FinFET with EUV lithography[5]
Transistors per die Approximately 8 billion[13] Approximately 18 billion[8]
Maximum active SMT8 cores per die 12[13] 15[8]
Maximum hardware threads per SMT8 die 96 120
L1 instruction cache 64 KiB per SMT8 core[13] 96 KiB per SMT8 core[6]
L1 data cache 64 KiB per SMT8 core[13] 64 KiB per SMT8 core[12]
L2 cache 512 KiB per core[13] 2 MiB per core[8]
Maximum L3 cache per die 120 MiB eDRAM[13] 120 MiB SRAM[8]
Main-memory attachment Direct DDR4 on scale-out designs or buffered memory on scale-up designs[13] OMI to external OMI-to-DDR controllers[8]
PCI Express 4.0[13] 5.0[8]
Power ISA version 3.0 3.1
Matrix acceleration No MMA facility Four MMA units per SMT8 core[14]
Known fully blob-free shipping configuration Yes, in Raptor systems[21] No

Systems

IBM introduced the following Power10-based systems. Maximum configured core counts refer to the largest documented processor configuration for the model and can differ from the number of licensed or activated cores.

System Class Maximum configured cores Notes
Power E1080 Enterprise scale-up 240 Up to 16 sockets and up to 64 TB of memory.[8]
Power E1050 Enterprise midrange 96 Four DCM sockets and up to 16 TB of memory; supports AIX and Linux workloads.[6]
Power S1024 Scale-out, 4U 48 One- or two-socket system with up to 24 cores per socket and up to 8 TB of memory.[7]
Power S1022 Scale-out, 2U 40 One- or two-socket DCM system with 12-, 16- or 20-core processor offerings.[7]
Power S1022s Scale-out, 2U 16 One- or two-socket eSCM system with four or eight cores per socket.[7]
Power S1014 Entry scale-out, 4U or tower 24 Single-socket system. Current documentation includes four- and eight-core eSCM and 24-core DCM configurations.[7]
Power S1012 Entry and edge 8 Single-socket half-width 2U or tower system with one, four or eight cores and up to 256 GB of DDR4 memory.[11]
Power L1024 Linux-oriented scale-out, 4U 48 Two-socket Linux-oriented counterpart to the S1024, with 12-, 16- or 24-core modules.[15]
Power L1022 Linux-oriented scale-out, 2U 40 Linux-oriented counterpart to the S1022, with up to two 20-core DCMs.[23][7]
IBM Power Virtual Server Cloud Varies Power10-based logical partitions have been offered through IBM's managed Power Virtual Server service.

Operating systems and virtualization

Power10 systems support AIX, IBM i and selected Linux distributions, with the exact operating-system matrix depending on server model. The E1050 and L-series systems are oriented toward AIX and/or Linux, while the S-series and E1080 cover broader AIX, IBM i and Linux use cases.[6][7][11]

Current Linux distributions for production Power10 systems use the 64-bit little-endian ppc64le architecture. AIX and IBM i use big-endian Power execution environments. Power10 also provides POWER9 and POWER8 processor-compatibility modes to support software compatibility and Live Partition Mobility scenarios.[8]

PowerVM is IBM's principal production virtualization environment for Power10. It provides logical partitioning, shared and dedicated processors, virtual I/O through VIOS, dynamic resource changes, shared processor and memory pools, and Live Partition Mobility.[16]

Linux supports Power10 processor identification and architecture facilities. QEMU implements both a Power10 CPU model and a powernv10 bare-metal machine model. The QEMU model is useful for firmware and operating-system development but is not a complete representation of every Power10 hardware and firmware component.[1][22][2]

Branding

IBM announced the processor as POWER10 in 2020. With the commercial server launch in 2021, IBM changed the product-family styling to Power10, with only the initial letter capitalized. IBM's current server, support and Redbooks documentation generally uses the Power10 form, while source code, architecture material and historical references frequently retain POWER10.[3][4][24]

References

  1. ↑ 1.0 1.1 1.2 PowerPC processor-version definitions, Linux kernel source.
  2. ↑ 2.0 2.1 2.2 PowerPC CPU model definitions and PowerPC CPU model registrations, QEMU source.
  3. ↑ 3.0 3.1 3.2 3.3 IBM Reveals Next-Generation IBM POWER10 Processor, IBM Newsroom, August 17, 2020.
  4. ↑ 4.0 4.1 4.2 4.3 IBM unveils new generation of IBM Power servers for frictionless, scalable hybrid cloud, IBM Newsroom, September 8, 2021.
  5. ↑ 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 5.09 5.10 5.11 William Starke et al., IBM's POWER10 Processor, Hot Chips 32, August 2020.
  6. ↑ 6.00 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.10 6.11 6.12 IBM Power E1050: Technical Overview and Introduction, IBM Redbooks, REDP-5684, updated 2024.
  7. ↑ 7.00 7.01 7.02 7.03 7.04 7.05 7.06 7.07 7.08 7.09 7.10 7.11 IBM Power10 Scale-Out Servers Technical Overview: S1012, S1014, S1022s, S1022 and S1024, IBM Redbooks, REDP-5675, updated 2025.
  8. ↑ 8.00 8.01 8.02 8.03 8.04 8.05 8.06 8.07 8.08 8.09 8.10 8.11 8.12 8.13 8.14 8.15 IBM Power E1080: Technical Overview and Introduction, IBM Redbooks, REDP-5649, updated 2024.
  9. ↑ IBM Expands Power10 Server Family, IBM Newsroom, July 12, 2022.
  10. ↑ IBM Introduces New IBM Power S1012, IBM Newsroom, May 7, 2024.
  11. ↑ 11.0 11.1 11.2 11.3 11.4 11.5 11.6 IBM Power S1012 Introduction, IBM Redbooks, REDP-5728, 2024.
  12. ↑ 12.0 12.1 SPEC CPU2017 result: IBM Power E1050, Standard Performance Evaluation Corporation, 2022.
  13. ↑ 13.0 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 IBM Power System E980: Technical Overview and Introduction, IBM Redbooks, REDP-5510.
  14. ↑ 14.0 14.1 José E. Moreira et al., A matrix math facility for Power ISA processors, 2021.
  15. ↑ 15.0 15.1 IBM Power L1024 data sheet, IBM, March 2024.
  16. ↑ 16.0 16.1 Introduction to IBM PowerVM, IBM Redbooks, SG24-8535.
  17. ↑ 17.0 17.1 IBM Power Security Catalog, IBM Redbooks, SG24-8568.
  18. ↑ 18.0 18.1 Michael Larabel, Not All Of The IBM POWER10 Firmware Is Currently Open-Source, Phoronix, September 8, 2021.
  19. ↑ 19.0 19.1 ClassicHasClass, It's not just OMI that's the trouble with POWER10, Talospace, September 8, 2021.
  20. ↑ Hugo Landau, In the future, even your RAM will have firmware; and the subject of POWER10 blobs.
  21. ↑ 21.0 21.1 21.2 21.3 Peter Czanik, Raptor CS: Fully Owner Controlled Computing using OpenPOWER, interview with Timothy Pearson, May 17, 2022.
  22. ↑ 22.0 22.1 22.2 PowerNV family boards (powernv8, powernv9, powernv10, powernv11), QEMU documentation.
  23. ↑ IBM Power L1022 documentation, IBM Documentation.
  24. ↑ Power10 First Look, POWERWire, September 8, 2021.

See also

External links

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