Difference between revisions of "POWER9"
(→Modules: The P9' is called Axone)
(→Pairing: Clarify that not all 8-core configurations are unpaired)
|(4 intermediate revisions by the same user not shown)|
|Line 22:||Line 22:|
POWER9 is IBM's most recent POWER compatible server and workstation CPU ([[Power ISA|POWER ISA]] v3.0B). Built on a 14nm process, each CPU package can contain up to 24 [[SMT4|SMT4]] cores or 12 [[SMT8|SMT8]] cores. Each pair of [[SMT4|SMT4]] cores, or singleton [[SMT8|SMT8]] core, comprises a slice; each slice in turn contains 512kB L2 cache and 10MB L3 cache.
POWER9 is IBM's most recent POWER compatible server and workstation CPU ([[Power ISA|POWER ISA]] v3.0B). Built on a 14nm process, each CPU package can contain up to 24 [[SMT4|SMT4]] cores or 12 [[SMT8|SMT8]] cores. Each pair of [[SMT4|SMT4]] cores, or singleton [[SMT8|SMT8]] core, comprises a slice ; each slice in turn contains 512kB L2 cache and 10MB L3 cache.
'and processorsprovide unpaired cores, such that one [[SMT4|SMT4]] core per slice is fused off. This allows each of the [[SMT4|SMT4]] cores to utilize the full cache of the slice exclusively, increasing performance for these [[Single_Thread|ST]]-focused processors.
Revision as of 02:08, 5 September 2022
|Maximum cores||12 SMT8 / 24 SMT4|
|L2 cache / slice||512kB|
|L3 cache / slice||10MB|
|Production availability||January 2018|
|Production stepping(s)||(Nimbus) DD2.2, DD2.3|
|← POWER8E||POWER10 →|
POWER9 is IBM's most recent POWER compatible server and workstation CPU (POWER ISA v3.0B). Built on a 14nm process, each CPU package can contain up to 24 SMT4 cores or 12 SMT8 cores. Each pair of SMT4 cores, or singleton SMT8 core, comprises a slice (some IBM documentation appears to call slices "chiplets"); each slice in turn contains 512kB L2 cache and 10MB L3 cache.
Most POWER9 processors share each slice's L2 and L3 cache between cores within the slice. However, some Sforza processors provide unpaired cores, such that one SMT4 core per slice is fused off. This allows each of the SMT4 cores to utilize the full cache of the slice exclusively, increasing performance for these ST-focused processors. There are also some security implications to whether cores are paired or unpaired.
POWER9 is fabricated using the GlobalFoundries 14HP (High Performance) process. This is distinct from the GlobalFoundries 14LPP (Low Power) process used by other GF 14nm customers, and is believed to be an IBM-specific process using ex-IBM Microelectronics intellectual property. The process is also used for the CPUs in IBM's z14 mainframes.
There are three known silicon masks of POWER9:
- Nimbus (POWER9 Scale Out)
- Cumulus (POWER9 Scale Up)
- Axone (POWER9′ ("POWER9 Prime"), aka POWER9 with Advanced I/O)
Chips can be fused as SMT4 or SMT8 during manufacturing. The SMT8 variant essentially fuses each pair of cores into one “core”, halving the core count while doubling the number of threads per core. SMT4 variants are intended for PowerNV platforms running Linux, and SMT8 variants are intended for use with IBM's PowerVM hypervisor which can run Linux, AIX or IBM i.
Several revisions of the Nimbus mask have been issued:
- DD 2.1 was the final preproduction revision before GA. It has errata preventing the use of hardware virtualization, but DD 2.1 Sforza can be used in e.g. the Talos II if this functionality is not needed.
- DD 2.2 is the first GA revision of Nimbus. DD 2.2 Sforza is sold by RCS as simply "POWER9", implying version 1.
- DD 2.3 is an updated revision of Nimbus, adding Ultravisor functionality, Hardware watchpoint support, and improved Meltdown and Spectre mitigations. DD 2.3 parts are sold by RCS as "POWER9 v2".
|Chip||Module||Memory Channels||XBUS Lanes||PCIe Lanes||OpenCAPI Lanes||Socket|
|Cumulus||(unknown)||(memory attached via Centaurs)||(unknown)||(unknown)||(unknown)||?|
|Axone||(unknown)||(memory attached via OMI)||Up to 3||Up to 48||Up to 48||?|
XBUS is used for inter-processor communication on dual-socket system
Nimbus chips are available in three different modules: Sforza, Monza, and LaGrange. Each module uses the same silicon mask but is packaged differently, exposing different I/O functionality to the host platform, allowing purpose-built systems to be constructed in addition to more general-purpose computers.
Sforza is the most flexible of these packages, providing PCIe 4.0 lanes as the main I/O resource, and is what Talos™ II uses for maximal similarity to existing desktop, workstation, and server systems.
Monza modules offer the most OpenCAPI/NVLink bandwidth and are used in IBM's AC922 (Witherspoon) systems, such as those used by the Sierra and Summit supercomputers.
Part numbers for different POWER9 Sforza SKUs can be found on page 58 of the datasheet. These part numbers are printed on the surface of the CPU module and can be used to determine the type of the CPU.
Little is known about Cumulus chips at this time; as Scale Up chips, they will trade some I/O bandwidth for support for more than two sockets.
Branded POWER9′ ("POWER9 Prime"), also known as POWER9 with Advanced I/O. Newly announced in August 2019. Uses serial memory attachment via OMI, an evolution from the Centaur.
- Schor, David. GlobalFoundries 14HP process, a marriage of two technologies. Wikichip Fuse.
- Stuecheli, Jeff. POWER9. Presentation for AIX VUG. (video download, slides, timemarks)
- Gangidi, Adi Zaius/Barreleye G2 Server Development Update. 2017-11-13
- Morgan, Timothy Prickett. POWER9 to the People. 2017-12-05
- POWER9 CPU and Platform Documentation
- POWER9 Hardware Compatibility List
- Basic POWER9 overview presentation
- Power ISA version 3.0B - implemented by POWER9