Difference between revisions of "Power ISA/Vector Operations"
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According to [[File:POWER9-Features-and-Specifications.pdf]] page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads). This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient. It is possible that clever usage of <code>taskset</code> may improve this situation. | According to [[File:POWER9-Features-and-Specifications.pdf]] page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads). This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient. It is possible that clever usage of <code>taskset</code> may improve this situation. | ||
| − | Power ISA v3.1 adds an optional VSX extension, MMA, targeted at matrix math applications. | + | Power ISA v3.1 adds an optional VSX extension, MMA (Matrix-Multiply Assist), targeted at matrix math applications. |
== External Links == | == External Links == | ||
| Line 27: | Line 27: | ||
== Github / Gitlab pages == | == Github / Gitlab pages == | ||
| + | |||
| + | === Translation from other architectures === | ||
| + | |||
| + | Implementations of non-POWER instruction sets for POWER. | ||
| + | |||
| + | * [https://github.com/gcc-mirror/gcc/blob/master/gcc/config/rs6000 GCC]. x86 to VSX. | ||
| + | * [https://github.com/llvm/llvm-project/tree/main/clang/lib/Headers/ppc_wrappers Clang]. x86 to VSX. | ||
| + | * [https://github.com/simd-everywhere/simde SIMD Everywhere]. x86/ARM/WASM to VSX (and other arches). | ||
| + | |||
| + | === Other === | ||
* Eigen. [https://gitlab.com/libeigen/eigen A C++ template library for linear algebra: matrices, vectors, numerical solvers and related algorithms] | * Eigen. [https://gitlab.com/libeigen/eigen A C++ template library for linear algebra: matrices, vectors, numerical solvers and related algorithms] | ||
* Simd Library. [https://github.com/ermig1979/Simd C++ image processing and machine learning library with using of SIMD] | * Simd Library. [https://github.com/ermig1979/Simd C++ image processing and machine learning library with using of SIMD] | ||
| − | |||
* EVE - the Expressive Vector Engine. [https://github.com/jfalcou/eve SIMD in C++] | * EVE - the Expressive Vector Engine. [https://github.com/jfalcou/eve SIMD in C++] | ||
* UniSIMD Assembler. [https://github.com/VectorChief/UniSIMD-assembler SIMD macro assembler unified for ARM, MIPS, PPC and x86] | * UniSIMD Assembler. [https://github.com/VectorChief/UniSIMD-assembler SIMD macro assembler unified for ARM, MIPS, PPC and x86] | ||
Latest revision as of 03:43, 2 October 2024
The Power Architecture ISA includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external standard, called Altivec by Freescale (Motorola spin-off), Vector Multimedia Extension (VMX) by IBM, and Velocity Engine by Apple.
The Vector operations are classified as Vector Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.
Power ISA v2.07 still refers to some instructions as VMX in its summary of changes since the previous version, but the rest of the document avoids mentioning VMX completely.
Power ISA v3.0 no longer mentions VMX at all.
According to File:POWER9-Features-and-Specifications.pdf page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads). This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient. It is possible that clever usage of taskset may improve this situation.
Power ISA v3.1 adds an optional VSX extension, MMA (Matrix-Multiply Assist), targeted at matrix math applications.
Contents
External Links
- Seebach, Peter. Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit. Published March 01, 2005
- Seebach, Peter. Unrolling AltiVec, Part 2, Optimize code for SIMD processing. Published March 16, 2005
- Gschwind, Michael. Workload acceleration with the IBM POWER vector-scalar architecture. IBM Journal of Research and Development. Published March, 2016
- Clarke, Paul. Vectorizing for fun and performance. Published January 24, 2018
- OpenPOWER. Vector Intrinsics Porting Guide. Published March 13, 2018
- Talospace. Easier Power ISA vectorizing for fun and profit with GCC x86 intrinsics. Published July 26, 2019
- OpenPOWER. Vector Intrinsics Programming Reference Specification. Published August 11, 2020
- Ruzhu Chen. Linux on IBM Power Systems application porting and tuning guide. Published September 27, 2020
- OpenPOWER. Vector Intrinsic Programming Reference Compliance Specification. Published March 28, 2021
- José E. Moreira. A matrix math facility for Power ISA(TM) processors. Published April 7, 2021
- José E. Moreira. Matrix-Multiply Assist Best Practices Guide. Published April 15, 2021
- Sridhar Venkat. MMA in IBM Power10 processor. Published August 29, 2022
Github / Gitlab pages
Translation from other architectures
Implementations of non-POWER instruction sets for POWER.
- GCC. x86 to VSX.
- Clang. x86 to VSX.
- SIMD Everywhere. x86/ARM/WASM to VSX (and other arches).
Other
- Eigen. A C++ template library for linear algebra: matrices, vectors, numerical solvers and related algorithms
- Simd Library. C++ image processing and machine learning library with using of SIMD
- EVE - the Expressive Vector Engine. SIMD in C++
- UniSIMD Assembler. SIMD macro assembler unified for ARM, MIPS, PPC and x86
- Turbo Base64. Fastest Base64 SIMD:SSE/AVX2/AVX512/Neon/Altivec
- Inastemp. Intrinsics as template - is a basic library to use vectorization easily in C++
- libsimdpp. Portable header-only C++ low level SIMD library
- pveclib. Power Vector Library
- SLEEF. SIMD Library for Evaluating Elementary Functions, vectorized libm and DFT
- libjpeg-turbo. A JPEG image codec that uses SIMD instructions to accelerate baseline JPEG compression and decompression
- libfreevec. SIMD optimized C library
