Difference between revisions of "POWER10"
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| + | {{Infobox | ||
| + | |title = Processor Information | ||
| + | |header1 = POWER10 | ||
| + | |label2 = [[Power ISA|Power ISA]] | ||
| + | |data2 = 3.1<ref name="cutressihc32">Cutress, Ian. [https://www.anandtech.com/show/15985/hot-chips-2020-live-blog-ibms-power10-processor-on-samsung-7nm-1000am-pt Hot Chips 2020 Live Blog: IBM's POWER10 Processor on Samsung 7nm (10:00am PT)]. ''Anandtech''. 2020-08-17</ref> | ||
| + | |label3 = Process node | ||
| + | |data3 = Samsung 7nm<ref name="cutressihc32"/> | ||
| + | |label4 = Maximum slices | ||
| + | |data4 = | ||
| + | |label5 = Maximum cores | ||
| + | |data5 = 15 [[SMT8|SMT8]] / 30 [[SMT4|SMT4]] | ||
| + | |label6 = L2 cache / slice | ||
| + | |data6 = | ||
| + | |label7 = L3 cache / slice | ||
| + | |data7 = | ||
| + | |label8 = Production availability | ||
| + | |data8 = | ||
| + | |label9 = Production stepping(s) | ||
| + | |data9 = | ||
| + | |label10 = [[POWER9|← POWER9]] | ||
| + | |data10 = [[POWER11|POWER11 →]] | ||
| + | }} | ||
| + | |||
While very little public information is currently available about '''POWER10''', initial support being added to the QEMU emulator suggests that it will be implementing the yet (as of 2020-05) unreleased Power ISA 3.10 or later.<ref>ClassicHasClass. [https://www.talospace.com/2020/05/qemu-adds-power10-support.html QEMU ADDS POWER10 SUPPORT]. ''Talospace''. 2020-05-03.</ref> | While very little public information is currently available about '''POWER10''', initial support being added to the QEMU emulator suggests that it will be implementing the yet (as of 2020-05) unreleased Power ISA 3.10 or later.<ref>ClassicHasClass. [https://www.talospace.com/2020/05/qemu-adds-power10-support.html QEMU ADDS POWER10 SUPPORT]. ''Talospace''. 2020-05-03.</ref> | ||
| + | |||
| + | Some details were revealed at the HotChips conference, see <ref>[https://regmedia.co.uk/2020/08/17/ibm_power10_summary.pdf slides], ''TheRegister''. 2020-08-17.</ref> | ||
== References == | == References == | ||
<references/> | <references/> | ||
| + | |||
| + | == External Links == | ||
| + | |||
| + | * [https://newsroom.ibm.com/2020-08-17-IBM-Reveals-Next-Generation-IBM-POWER10-Processor IBM Announcement] | ||
| + | * [https://www.theregister.com/2020/08/17/ibm_t7nm_power10/ TheRegister.com] | ||
| + | * [https://www.nextplatform.com/2020/08/18/ibm-brings-an-architecture-gun-to-a-chip-knife-fight/ TheNextPlatform.com] | ||
Latest revision as of 17:15, 21 August 2020
| POWER10 | |
|---|---|
| Power ISA | 3.1[1] |
| Process node | Samsung 7nm[1] |
| Maximum cores | 15 SMT8 / 30 SMT4 |
| ← POWER9 | POWER11 → |
While very little public information is currently available about POWER10, initial support being added to the QEMU emulator suggests that it will be implementing the yet (as of 2020-05) unreleased Power ISA 3.10 or later.[2]
Some details were revealed at the HotChips conference, see [3]
References
- ↑ 1.0 1.1 Cutress, Ian. Hot Chips 2020 Live Blog: IBM's POWER10 Processor on Samsung 7nm (10:00am PT). Anandtech. 2020-08-17
- ↑ ClassicHasClass. QEMU ADDS POWER10 SUPPORT. Talospace. 2020-05-03.
- ↑ slides, TheRegister. 2020-08-17.
