Difference between revisions of "Power ISA/Vector Operations"

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The Power Architecture ISA includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external standard, called Altivec by Freescale (Motorola spin-off), Vector Multimedia Extension (VMX) by IBM, and Velocity Engine by Apple.
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The [[Power ISA]] includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external standard, called Altivec by Freescale (Motorola spin-off), Vector Multimedia Extension (VMX) by IBM, and Velocity Engine by Apple.
  
 
The Vector operations are classified as Vector Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.
 
The Vector operations are classified as Vector Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.
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According to [[File:POWER9-Features-and-Specifications.pdf]] page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads).  This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient.  It is possible that clever usage of <code>taskset</code> may improve this situation.
 
According to [[File:POWER9-Features-and-Specifications.pdf]] page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads).  This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient.  It is possible that clever usage of <code>taskset</code> may improve this situation.
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Power ISA v3.1 adds an optional VSX extension, MMA (Matrix-Multiply Assist), targeted at matrix math applications.
  
 
== External Links ==
 
== External Links ==
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* Seebach, Peter. [https://web.archive.org/web/20080614023936/https://www.ibm.com/developerworks/library/pa-unrollav1/ Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit]. Published March 01, 2005
 
* Seebach, Peter. [https://web.archive.org/web/20080614023936/https://www.ibm.com/developerworks/library/pa-unrollav1/ Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit]. Published March 01, 2005
 
* Seebach, Peter. [https://www.sucs.org/~grepwood/ps3/altivec/pa-unrollav2-pdf.pdf Unrolling AltiVec, Part 2, Optimize code for SIMD processing]. Published March 16, 2005
 
* Seebach, Peter. [https://www.sucs.org/~grepwood/ps3/altivec/pa-unrollav2-pdf.pdf Unrolling AltiVec, Part 2, Optimize code for SIMD processing]. Published March 16, 2005
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* Gschwind, Michael. [https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture Workload acceleration with the IBM POWER vector-scalar architecture]. IBM Journal of Research and Development. Published March, 2016
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* Gschwind, Michael. [https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture Workload acceleration with the IBM POWER vector-scalar architecture]. Published March, 2016
 
* Clarke, Paul. [https://www.ibm.com/support/pages/vectorizing-fun-and-performance Vectorizing for fun and performance]. Published January 24, 2018
 
* Clarke, Paul. [https://www.ibm.com/support/pages/vectorizing-fun-and-performance Vectorizing for fun and performance]. Published January 24, 2018
 
* OpenPOWER. [https://openpowerfoundation.org/specifications/vectorintrinsicportingguide/ Vector Intrinsics Porting Guide]. Published March 13, 2018
 
* OpenPOWER. [https://openpowerfoundation.org/specifications/vectorintrinsicportingguide/ Vector Intrinsics Porting Guide]. Published March 13, 2018
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* Ruzhu Chen. [https://developer.ibm.com/learningpaths/port-your-app-to-lop/migrate-app-on-lop/ Linux on IBM Power Systems application porting and tuning guide]. Published September 27, 2020
 
* Ruzhu Chen. [https://developer.ibm.com/learningpaths/port-your-app-to-lop/migrate-app-on-lop/ Linux on IBM Power Systems application porting and tuning guide]. Published September 27, 2020
 
* OpenPOWER. [https://openpowerfoundation.org/compliance/vectorintrinsicprogrammingreference/ Vector Intrinsic Programming Reference Compliance Specification]. Published March 28, 2021
 
* OpenPOWER. [https://openpowerfoundation.org/compliance/vectorintrinsicprogrammingreference/ Vector Intrinsic Programming Reference Compliance Specification]. Published March 28, 2021
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* José E. Moreira. [https://arxiv.org/abs/2104.03142 A matrix math facility for Power ISA(TM) processors]. Published April 7, 2021
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* José E. Moreira. [https://www.redbooks.ibm.com/Redbooks.nsf/RedpieceAbstracts/redp5612.html Matrix-Multiply Assist Best Practices Guide]. Published April 15, 2021
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* Sridhar Venkat. [https://community.ibm.com/community/user/powerdeveloper/blogs/sridhar-venkat1/2022/08/29/power10-mma MMA in IBM Power10 processor]. Published August 29, 2022
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* VectorCamp. [https://simd.info/ SIMD.info], an online searchable reference tool for C intrinsics of all major SIMD engines (including VSX).
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* VectorCamp. [https://simd.ai/ Advanced SIMD Porting Intelligence]. LLM that helps optimize and port code to SIMD architectures in seconds.
  
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== Github pages ==
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== GitHub / GitLab pages ==
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[https://github.com/ermig1979/Simd C++ image processing and machine learning library with using of SIMD]
 
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[https://github.com/simd-everywhere/simde Implementations of SIMD instruction sets for systems which don't natively support them]
 
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[https://github.com/jfalcou/eve Expressive Vector Engine - SIMD in C++]
 
  
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[https://github.com/VectorChief/UniSIMD-assembler SIMD macro assembler unified for ARM, MIPS, PPC and x86]
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=== Translation from other architectures ===
  
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[https://github.com/powturbo/Turbo-Base64 Turbo Base64 - Fastest Base64 SIMD:SSE/AVX2/AVX512/Neon/Altivec]
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Implementations of non-POWER instruction sets for POWER.
  
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[https://github.com/berenger-eu/inastemp Intrinsics as template - is a basic library to use vectorization easily in C++]
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* [https://github.com/gcc-mirror/gcc/blob/master/gcc/config/rs6000 GCC]. x86 to VSX.
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* [https://github.com/llvm/llvm-project/tree/main/clang/lib/Headers/ppc_wrappers Clang]. x86 to VSX.
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* [https://github.com/simd-everywhere/simde SIMD Everywhere]. x86/ARM/WASM to VSX (and other arches).
  
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[https://github.com/p12tic/libsimdpp Portable header-only C++ low level SIMD library]
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=== SIMD libraries and frameworks ===
  
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[https://github.com/open-power-sdk/pveclib Power Vector Library]
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* Eigen. [https://gitlab.com/libeigen/eigen A C++ template library for linear algebra: matrices, vectors, numerical solvers and related algorithms]
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* EVE - the Expressive Vector Engine. [https://github.com/jfalcou/eve SIMD in C++]
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* Highway. [https://github.com/google/highway C++ library that provides portable SIMD/vector intrinsics]
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* Simd Library. [https://github.com/ermig1979/Simd C++ image processing and machine learning library with using of SIMD]
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* pveclib. [https://github.com/open-power-sdk/pveclib Power Vector Library]
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* UniSIMD Assembler. [https://github.com/VectorChief/UniSIMD-assembler SIMD macro assembler unified for ARM, MIPS, PPC and x86]
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* libsimdpp. [https://github.com/p12tic/libsimdpp Portable header-only C++ low level SIMD library]
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* inastemp. [https://gitlab.inria.fr/bramas/inastemp Intrinsics as template - is a basic library to use vectorization easily in C++]
  
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[https://github.com/shibatch/sleef SIMD Library for Evaluating Elementary Functions, vectorized libm and DFT]
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=== Specialized implementations ===
  
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[https://github.com/VectorCamp/libfreevec SIMD optimized C library]
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* simdutf. [https://github.com/simdutf/simdutf C++ library for fast Unicode transcoding using SIMD]
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* libjpeg-turbo. [https://github.com/libjpeg-turbo/libjpeg-turbo A JPEG image codec that uses SIMD instructions to accelerate baseline JPEG compression and decompression]
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* Vectorscan. [https://github.com/VectorCamp/vectorscan A portable fork of the high-performance regular expression matching library]
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* SLEEF. [https://github.com/shibatch/sleef SIMD Library for Evaluating Elementary Functions, vectorized libm and DFT]
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* Turbo Base64. [https://github.com/powturbo/Turbo-Base64 Fastest Base64 SIMD:SSE/AVX2/AVX512/Neon/Altivec]
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* Camellia cipher. [https://github.com/jkivilin/camellia-simd-aesni SIMD vector implementations ... for POWER (with VMX+VSX+crypto instructions)]
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* libvpx. [https://github.com/lu-zero/libvpx Video codec library with specific optimizations for ppc64le]
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* lamevmx. [https://github.com/classilla/lamevmx Altivec optimized MP3 encoder]
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* libfreevec. [https://github.com/VectorCamp/libfreevec SIMD optimized GNU C library]

Latest revision as of 15:12, 1 July 2025

The Power ISA includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external standard, called Altivec by Freescale (Motorola spin-off), Vector Multimedia Extension (VMX) by IBM, and Velocity Engine by Apple.

The Vector operations are classified as Vector Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.

Power ISA v2.07 still refers to some instructions as VMX in its summary of changes since the previous version, but the rest of the document avoids mentioning VMX completely.

Power ISA v3.0 no longer mentions VMX at all.

According to File:POWER9-Features-and-Specifications.pdf page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads). This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient. It is possible that clever usage of taskset may improve this situation.

Power ISA v3.1 adds an optional VSX extension, MMA (Matrix-Multiply Assist), targeted at matrix math applications.

External Links

GitHub / GitLab pages

Translation from other architectures

Implementations of non-POWER instruction sets for POWER.

SIMD libraries and frameworks

Specialized implementations

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