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Page title matches

  • Power NOR
    18 bytes (2 words) - 13:01, 19 December 2017
  • Power ISA
    '''Power ISA''' is the specification for how Power architecture processors are to behave. It dictates the machine instruction ...re two primary versions of the Power ISA that are of interest to [[PowerNV|PowerNV]] platforms:
    3 KB (449 words) - 09:50, 23 January 2024
  • POWER/Spectre Protections
    50 bytes (5 words) - 18:12, 6 March 2019
  • Troubleshooting/BMC Power
    ...ation on how to interrogate the FPGA for status information when low-level power faults occur. When troubleshooting power sequencing, start by reading the key registers from the BMC shell:
    5 KB (868 words) - 07:41, 19 January 2020
  • Power ISA/SIMD Operations
    #REDIRECT [[Power ISA/Vector Operations]]
    41 bytes (5 words) - 21:54, 26 May 2023
  • Configuring Power Restore States
    ...ns how to configure RCS [[OpenPOWER]] systems to power on immediately when power is applied to a system. All RCS [[OpenPOWER]] systems.
    1 KB (187 words) - 13:37, 2 March 2019
  • Power ISA/Vector Operations
    ...a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external stan ...ctor Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.
    5 KB (608 words) - 06:54, 8 November 2023
  • Power ISA/Privilege States
    ...support for Secure Virtual Machines (SVMs). It was first made available on POWER9 Nimbus chips with DD2.3 stepping. Like with Hypervisor State, Ultravisor S ...rg/patch/719952/</ref> It will probably be part of future revisions of the Power ISA.
    5 KB (729 words) - 21:09, 4 May 2020
  • Power ISA/Machine State Register
    ...Branch Facility register usually defined in Book III in of the [[Power ISA|Power ISA]]. Among other uses, the MSR contains information about the privilege l ...sions] and [https://www.devever.net/~hl/power9tags The Talos II, Blackbird POWER9 systems support tagged memory].</ref>
    13 KB (1,676 words) - 03:43, 7 November 2022
  • Talos II/Configure Power Restore States
    #REDIRECT [[Configuring Power Restore States]]
    46 bytes (5 words) - 13:37, 2 March 2019

Page text matches

  • PowerISA
    #REDIRECT [[Power ISA]]
    23 bytes (3 words) - 22:30, 19 January 2018
  • Power ISA/SIMD Operations
    #REDIRECT [[Power ISA/Vector Operations]]
    41 bytes (5 words) - 21:54, 26 May 2023
  • Privilege States
    #REDIRECT [[Power ISA/Privilege States]]
    40 bytes (5 words) - 10:50, 12 February 2018
  • Talos II/Configure Power Restore States
    #REDIRECT [[Configuring Power Restore States]]
    46 bytes (5 words) - 13:37, 2 March 2019
  • Machine State Register
    #REDIRECT [[Power ISA/Machine State Register]]
    46 bytes (6 words) - 10:51, 12 February 2018
  • MSR
    #REDIRECT [[Power ISA/Machine State Register]]
    46 bytes (6 words) - 10:56, 12 February 2018
  • S1
    ...[Solid Silicon]]'s first server and workstation OpenPOWER CPU ([[Power ISA|POWER ISA]] v3.1). It uses PCIe Gen 5<ref>[https://nitter.net/RaptorCompSys/statu
    293 bytes (38 words) - 07:42, 14 November 2023
  • Configuring Power Restore States
    ...ns how to configure RCS [[OpenPOWER]] systems to power on immediately when power is applied to a system. All RCS [[OpenPOWER]] systems.
    1 KB (187 words) - 13:37, 2 March 2019
  • GPE
    ...llary microprocessor on a [[POWER9]] chip which assists the [[OCC]] in its power management duties. Two types of GPE exist on [[POWER9]] chips:
    479 bytes (74 words) - 03:47, 4 November 2021
  • BMC
    ...a:IPMI|IPMI]] and performs necessary baseboard initialization prior to CPU power on. Monitors CPU temperatures and sets fan speeds appropriately.}}
    688 bytes (99 words) - 10:55, 2 December 2022
  • X1
    X1 is [[Solid Silicon]]'s first BMC. It is [[Power ISA]] compliant.<ref>[https://nitter.net/RaptorCompSys/status/1715233204037
    240 bytes (30 words) - 23:29, 14 November 2023
  • Porting/RandomX
    * [https://github.com/tevador/RandomX/pull/41 Added POWER7+ intrinsincs and cpu detection to makefile] * [https://github.com/tevador/RandomX/issues/132 POWER support]
    1 KB (157 words) - 22:07, 2 February 2021
  • PPC405
    |header1 = PowerPC 405 |label2 = [[Power ISA|Power ISA]]
    869 bytes (120 words) - 11:01, 12 February 2018
  • IPL
    ...program load. The process by which IBM computers are brought from a cold power off state to a functional bootloader environment. Equivalent to the x86 "b
    224 bytes (34 words) - 10:04, 20 December 2017
  • Microcode
    ...s are hardcoded. There are some auxillary microprocessors on-die to handle power management functions (the [[CME]], [[SGPE]] and [[PGPE]], as well as the [[ * [https://github.com/open-power/hcode Source code for POWER9 power management cores]
    606 bytes (84 words) - 14:47, 19 December 2017
  • OCC
    ...allow it to set appropriate fan speeds. The OCC implements any applicable power caps and supports programmable TDP limits.}} The [[CME]], [[SGPE]] and [[PGPE]] auxillary microprocessors handle various power management responsibilities and are managed by the OCC.
    1 KB (139 words) - 03:19, 22 February 2018
  • Magewell/ProCapture
    == POWER Drivers == ...to provide perfect A/V sync for studio applications. This enhancement is POWER-exclusive; builds of the modified PerfectSync driver stack are not availabl
    2 KB (246 words) - 06:29, 9 December 2019
  • PNOR
    |name=Power NOR
    298 bytes (46 words) - 12:57, 19 December 2017
  • Porting/Docker
    == Docker on POWER == Docker runs fine on POWER, the only issues are with golang on big endian ppc64, which does not suppor
    814 bytes (114 words) - 17:46, 10 March 2023
  • PowerNV
    |name=PowerNV |abbr=PowerNV
    798 bytes (118 words) - 01:27, 22 December 2017

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