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• Murano
  |label7 = PCIe controllers ([[PEC|PEC]])
  533 bytes (67 words) - 14:24, 2 March 2019
• Turismo
  |label7 = PCIe controllers ([[PEC|PEC]])
  912 bytes (111 words) - 00:10, 20 September 2022
• Monza
  |label7 = PCIe controllers ([[PEC|PEC]])
  2 KB (277 words) - 08:02, 8 September 2022
• LaGrange
  |label7 = PCIe controllers ([[PEC|PEC]])
  3 KB (322 words) - 09:54, 6 September 2022
• Sforza
  |label7 = PCIe controllers ([[PEC|PEC]])
  6 KB (830 words) - 00:26, 20 September 2022
• POWER9 Hardware Compatibility List/PCIe Devices
  * '''Incomplete memory addressing support.''' The PCIe architecture specifies a 64-bit address space. Some I/O devices try to economize on this by o ...h 4KiB and 64KiB page sizes]]; x86 is 4KiB only. Some buggy drivers may expect one and break in the other.
  60 KB (9,019 words) - 16:02, 10 April 2024