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- 21:12, 30 July 2020 diff hist -421 Main Page pruning old events
- 21:10, 30 July 2020 diff hist +584 Main Page separating out community links and formatting for readability, adding link to virtual coffee calls
- 13:38, 6 July 2020 diff hist 0 m Talk:POWER9 →Stepping DD 2.0 (or prior) information current
- 13:38, 6 July 2020 diff hist +519 Talk:POWER9 →Stepping DD 2.0 (or prior) information: new section
- 13:31, 6 July 2020 diff hist +24 POWER9 →Steppings: formatting to match data sheet and other IBM documentation formatting
- 12:55, 6 July 2020 diff hist +128 LaGrange link to datasheet
- 21:29, 4 May 2020 diff hist +1 m POWER10
- 21:28, 4 May 2020 diff hist +407 N POWER10 Initial info from Talospace from QEMU patches
- 21:20, 4 May 2020 diff hist +11 POWER9 Add P10 link
- 21:09, 4 May 2020 diff hist +213 Power ISA/Privilege States →Ultravisor State: rewriting for the present, additional information current
- 20:57, 4 May 2020 diff hist +108 Power ISA/Machine State Register →Privilege State: reference dedicated page for this
- 20:50, 4 May 2020 diff hist +1 m Power ISA/Machine State Register →= Privilege State: oops missing character
- 20:49, 4 May 2020 diff hist +381 Power ISA/Machine State Register →Combined: rename section add preliminary description for privilege state section
- 18:12, 4 May 2020 diff hist +146 Power ISA/Machine State Register Add s bit to table
- 18:03, 4 May 2020 diff hist +62 Power ISA/Machine State Register →Combined: ref section, prep adding s bit information to privilege table
- 17:52, 4 May 2020 diff hist +289 Power ISA/Machine State Register →Map: I found the Ultravisor bit!
- 17:40, 4 May 2020 diff hist +9 m POWER9 Stepping is not necessarily the same for cumulus chips (and certainly not Axone/AIO)
- 17:37, 4 May 2020 diff hist -3 m Condor Move ref
- 17:35, 4 May 2020 diff hist +44 Condor →External Links: transition to references
- 17:31, 4 May 2020 diff hist +70 Condor →See also: clarify differences add blackbird link