Difference between revisions of "Power ISA/Vector Operations"

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(Created page with "The Power Architecture ISA includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in...")
 
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== External Links ==
 
== External Links ==
  
* [https://www.ibm.com/developerworks/library/pa-unrollav1/ Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit]
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* Seebach, Peter. [https://www.ibm.com/developerworks/library/pa-unrollav1/ Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit]
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* Gschwind, Michael. [https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture Workload acceleration with the IBM POWER vector-scalar architecture]. IBM Journal of Research and Development

Revision as of 11:16, 12 February 2018

The Power Architecture ISA includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external standard, called Altivec by Motorola (and then Freescale who bought them), VMX by IBM, and Velocity Engine by Apple.

The Vector operations are classified as Vector Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.

Power ISA v2.07 still refers to some instructions as VMX in its summary of changes since the previous version, but the rest of the document avoids mentioning VMX completely.

Power ISA v3 no longer mentions VMX at all.

External Links