Difference between revisions of "Power ISA/Vector Operations"
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== External Links == | == External Links == | ||
| − | * Seebach, Peter. [https://www.ibm.com/developerworks/library/pa-unrollav1/ Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit]. Published March 01, 2005 | + | * Seebach, Peter. [https://web.archive.org/web/20080614023936/https://www.ibm.com/developerworks/library/pa-unrollav1/ Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit]. Published March 01, 2005 |
| − | * Seebach, Peter. [https://www. | + | * Seebach, Peter. [https://www.sucs.org/~grepwood/ps3/altivec/pa-unrollav2-pdf.pdf Unrolling AltiVec, Part 2, Optimize code for SIMD processing (PDF)]. Published March 16, 2005 |
* Gschwind, Michael. [https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture Workload acceleration with the IBM POWER vector-scalar architecture]. IBM Journal of Research and Development. Published March, 2016 | * Gschwind, Michael. [https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture Workload acceleration with the IBM POWER vector-scalar architecture]. IBM Journal of Research and Development. Published March, 2016 | ||
* Clarke, Paul. [https://www.ibm.com/support/pages/vectorizing-fun-and-performance Vectorizing for fun and performance]. Published January 24, 2018 | * Clarke, Paul. [https://www.ibm.com/support/pages/vectorizing-fun-and-performance Vectorizing for fun and performance]. Published January 24, 2018 | ||
Revision as of 14:48, 7 May 2023
The Power Architecture ISA includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external standard, called Altivec by Freescale (Motorola spin-off), Vector Multimedia Extension (VMX) by IBM, and Velocity Engine by Apple.
The Vector operations are classified as Vector Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.
Power ISA v2.07 still refers to some instructions as VMX in its summary of changes since the previous version, but the rest of the document avoids mentioning VMX completely.
Power ISA v3.0 no longer mentions VMX at all.
According to File:POWER9-Features-and-Specifications.pdf page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads). This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient. It is possible that clever usage of taskset may improve this situation.
External Links
- Seebach, Peter. Unrolling AltiVec, Part 1, Introducing the PowerPC SIMD unit. Published March 01, 2005
- Seebach, Peter. Unrolling AltiVec, Part 2, Optimize code for SIMD processing (PDF). Published March 16, 2005
- Gschwind, Michael. Workload acceleration with the IBM POWER vector-scalar architecture. IBM Journal of Research and Development. Published March, 2016
- Clarke, Paul. Vectorizing for fun and performance. Published January 24, 2018
- OpenPOWER. Vector Intrinsics Porting Guide. Published March 13, 2018
- Talospace. Easier Power ISA vectorizing for fun and profit with GCC x86 intrinsics. Published July 26, 2019
- OpenPOWER. Vector Intrinsics Programming Reference Specification. Published August 11, 2020
- Ruzhu Chen. Linux on IBM Power Systems application porting and tuning guide. Published September 27, 2020
- OpenPOWER. Vector Intrinsic Programming Reference Compliance Specification. Published March 28, 2021
