Power ISA
Power ISA is the specification for how Power architecture processors are to behave. It dictates the machine instructions available, and exactly how they are to process given data.
There are two primary versions of the Power ISA that are of interest to PowerNV platforms:
History
The Power ISA evolved from the PowerPC ISA which in turn was an evolution of the POWER ISA used by POWER1 and POWER2 chips.
POWER ISA → PowerPC ISA → Power ISA
When the Power ISA 3.0B specification lists all available instructions, it specifically mentions what version of which architecture introduced the instruction; this gives a fairly quick history of the ISA itself:
| Code | Explanation |
|---|---|
| P1 | Instruction introduced in the POWER Architecture. |
| P2 | Instruction introduced in the POWER2 Architecture. |
| PPC | Instruction introduced in the PowerPC Architecture prior to v2.00. |
| v2.00 | Instruction introduced in the PowerPC Architecture Version 2.00. |
| v2.01 | Instruction introduced in the PowerPC Architecture Version 2.01. |
| v2.02 | Instruction introduced in the PowerPC Architecture Version 2.02. |
| v2.03 | Instruction introduced in the Power ISA Architecture Version 2.03. |
| v2.04 | Instruction introduced in the Power ISA Architecture Version 2.04. |
| v2.05 | Instruction introduced in the Power ISA Architecture Version 2.05. |
| v2.06 | Instruction introduced in the Power ISA Architecture Version 2.06. |
| v2.07 | Instruction introduced in the Power ISA Architecture Version 2.07. |
| v3.0 | Instruction introduced in the Power ISA Architecture Version 3.0. |
| v3.0B | Instruction introduced in the Power ISA Architecture Version 3.0B. |
Privilege Levels
- ultravisor privileged state
- hypervisor privileged state
- privileged state / supervisor mode
- problem state / user mode
At the moment very little information exists about the ultravisor state. It is not mentioned only in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible classification for instructions.
| Code | 2.07 | 3.0B | Description |
|---|---|---|---|
| P | Yes | Yes | a privileged instruction. |
| O | Yes | Yes | an instruction that is treated as privileged or nonprivileged (or hypervisor, for mtspr), depend-
ing on the SPR or PMR number. |
| PI | No | Yes | an instruction that is illegal in privileged state. |
| H | Yes | Yes | an instruction that can be executed only in hypervisor state |
| PH | Yes | No | a hypervisor privileged instruction if Category Embedded.Hypervisor is implemented; otherwise
denotes a privileged instruction. |
| M | Yes | No | an instruction that is treated as privileged or nonprivileged, depending on the value of the UCLE
bit in the MSR |
| U | No | Yes | an instruction that can be executed only in ultravisor state |
