Difference between revisions of "POWER9"
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* [[:File:POWER9-Features-and-Specifications.pdf|Basic POWER9 overview presentation]] | * [[:File:POWER9-Features-and-Specifications.pdf|Basic POWER9 overview presentation]] | ||
| − | * [[:File:PowerISA_public.v3.0B.pdf| | + | * [[:File:PowerISA_public.v3.0B.pdf|Power ISA version 3.0B]] - implemented by POWER9 |
== External Links == | == External Links == | ||
Revision as of 09:06, 26 January 2018
| POWER9 | |
|---|---|
| Power ISA | 3.0B |
| Process node | 14nm |
| Maximum slices | 24 |
| Maximum cores | 12 SMT8 / 24 SMT4 |
| L2 cache / slice | 512kB |
| L3 cache / slice | 10MB |
| Production availability | January 2018 |
| Production stepping(s) | DD2.2 |
| ← POWER8E | POWER10 → |
POWER9 is IBM's most recent POWER compatible server and workstation CPU (POWER ISA v3.0B). Built on a 14nm process, each CPU package can contain up to 24 SMT4 cores or 12 SMT8 cores. Each pair of SMT4 cores, or singleton SMT8 core, comprises a slice; each slice in turn contains 512kB L2 cache and 10MB L3 cache. Raptor Computing Systems' 4- and 8-core processors provide unpaired cores, such that one SMT4 core per slice is fused off. This allows each of the SMT4 cores to utilize the full cache of the slice exclusively, increasing performance for these ST-focused processors.
| PowerNV | PowerVM | |
|---|---|---|
| Scale Out | Nimbus | unknown |
| Scale Up | Cumulus |
PowerNV systems use SMT4 packages exclusively, and are available in three different sockets of the Nimbus chip: Sforza, Monza, and LaGrange. Each socket type exposes different I/O functionality to the host platform, allowing purpose-built systems to be constructed in addition to more general-purpose computers. Sforza is the most flexible of these packages, providing PCIe 4.0 lanes as the main I/O resource, and is what Talos™ II uses for maximal similarity to existing desktop, workstation, and server systems.
PowerVM systems, in contrast, use SMT8 chips, and are intended to run Linux, AIX, or IBM i under IBM's PowerVM hypervisor. SMT8 chips are planned to be made in both Scale Out (direct-attach RAM) and Scale Up (centaur-buffered RAM) configurations.
Resources
- Basic POWER9 overview presentation
- Power ISA version 3.0B - implemented by POWER9
