Difference between revisions of "Power ISA/Vector Operations"

From RCS Wiki
Jump to navigation Jump to search
Line 23: Line 23:
 
== Github / Gitlab pages ==
 
== Github / Gitlab pages ==
  
* [https://gitlab.com/libeigen/eigen Eigen is a C++ template library for linear algebra: matrices, vectors, numerical solvers and related algorithms]
+
* Eigen. [https://gitlab.com/libeigen/eigen A C++ template library for linear algebra: matrices, vectors, numerical solvers and related algorithms]
* [https://github.com/ermig1979/Simd C++ image processing and machine learning library with using of SIMD]
+
* Simd Library. [https://github.com/ermig1979/Simd C++ image processing and machine learning library with using of SIMD]
* [https://github.com/simd-everywhere/simde Implementations of SIMD instruction sets for systems which don't natively support them]
+
* SIMD Everywhere. [https://github.com/simd-everywhere/simde Implementations of SIMD instruction sets for systems which don't natively support them]
* [https://github.com/jfalcou/eve Expressive Vector Engine - SIMD in C++]
+
* EVE - the Expressive Vector Engine. [https://github.com/jfalcou/eve SIMD in C++]
* [https://github.com/VectorChief/UniSIMD-assembler SIMD macro assembler unified for ARM, MIPS, PPC and x86]
+
* UniSIMD Assembler. [https://github.com/VectorChief/UniSIMD-assembler SIMD macro assembler unified for ARM, MIPS, PPC and x86]
* [https://github.com/powturbo/Turbo-Base64 Turbo Base64 - Fastest Base64 SIMD:SSE/AVX2/AVX512/Neon/Altivec]
+
* Turbo Base64. [https://github.com/powturbo/Turbo-Base64 Fastest Base64 SIMD:SSE/AVX2/AVX512/Neon/Altivec]
* [https://gitlab.inria.fr/bramas/inastemp Intrinsics as template - is a basic library to use vectorization easily in C++]
+
* Inastemp. [https://gitlab.inria.fr/bramas/inastemp Intrinsics as template - is a basic library to use vectorization easily in C++]
* [https://github.com/p12tic/libsimdpp Portable header-only C++ low level SIMD library]
+
* libsimdpp. [https://github.com/p12tic/libsimdpp Portable header-only C++ low level SIMD library]
* [https://github.com/open-power-sdk/pveclib Power Vector Library]
+
* pveclib. [https://github.com/open-power-sdk/pveclib Power Vector Library]
* [https://github.com/shibatch/sleef SIMD Library for Evaluating Elementary Functions, vectorized libm and DFT]
+
* SLEEF. [https://github.com/shibatch/sleef SIMD Library for Evaluating Elementary Functions, vectorized libm and DFT]
* [https://github.com/VectorCamp/libfreevec SIMD optimized C library]
+
* libfreevec. [https://github.com/VectorCamp/libfreevec SIMD optimized C library]

Revision as of 17:50, 15 June 2023

The Power Architecture ISA includes a specification of vector or SIMD operations. Prior to the Power ISA, i.e. PowerPC, some of these operations were available, but defined in an external standard, called Altivec by Freescale (Motorola spin-off), Vector Multimedia Extension (VMX) by IBM, and Velocity Engine by Apple.

The Vector operations are classified as Vector Facility and Vector Scalar Extension (VSX) in current versions of the Power ISA.

Power ISA v2.07 still refers to some instructions as VMX in its summary of changes since the previous version, but the rest of the document avoids mentioning VMX completely.

Power ISA v3.0 no longer mentions VMX at all.

According to File:POWER9-Features-and-Specifications.pdf page 7, the Vector Scalar Unit (VSU)'s 128-bit hardware is dedicated per super-slice (2 threads). This may indicate that trying to aggressively use 128-bit VSX instructions in two threads that use the same super-slice will be inefficient. It is possible that clever usage of taskset may improve this situation.

External Links

Github / Gitlab pages