Difference between revisions of "POWER9"
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=== Nimbus === | === Nimbus === | ||
| − | Nimbus chips are available in three different modules: [[Sforza]], [[Monza]], and [[LaGrange]]. Each module | + | Nimbus chips are available in three different modules: [[Sforza]], [[Monza]], and [[LaGrange]]. Each module uses the same silicon mask but is packaged differently, exposing different I/O functionality to the host platform, allowing purpose-built systems to be constructed in addition to more general-purpose computers. |
'''[[Sforza|Sforza]]''' is the most flexible of these packages, providing PCIe 4.0 lanes as the main I/O resource, and is what [[Talos_II|Talos™ II]] uses for maximal similarity to existing desktop, workstation, and server systems. | '''[[Sforza|Sforza]]''' is the most flexible of these packages, providing PCIe 4.0 lanes as the main I/O resource, and is what [[Talos_II|Talos™ II]] uses for maximal similarity to existing desktop, workstation, and server systems. | ||
Revision as of 17:48, 6 March 2019
| POWER9 | |
|---|---|
| Power ISA | 3.0B |
| Process node | 14nm |
| Maximum slices | 24 |
| Maximum cores | 12 SMT8 / 24 SMT4 |
| L2 cache / slice | 512kB |
| L3 cache / slice | 10MB |
| Production availability | January 2018 |
| Production stepping(s) | DD2.2 |
| ← POWER8E | POWER10 → |
POWER9 is IBM's most recent POWER compatible server and workstation CPU (POWER ISA v3.0B). Built on a 14nm process, each CPU package can contain up to 24 SMT4 cores or 12 SMT8 cores. Each pair of SMT4 cores, or singleton SMT8 core, comprises a slice; each slice in turn contains 512kB L2 cache and 10MB L3 cache. Raptor Computing Systems' 4- and 8-core processors provide unpaired cores, such that one SMT4 core per slice is fused off. This allows each of the SMT4 cores to utilize the full cache of the slice exclusively, increasing performance for these ST-focused processors.
Contents
Chips
There are three known silicon masks of POWER9:
Nimbus is the “scale out” variant and uses direct-attach DDR4 memory. Cumulus is the “scale up” version and uses Centaur memory buffers, allowing larger amounts of memory to be attached to a system.
Chips can be fused as SMT4 or SMT8 during manufacturing. The SMT8 variant essentially fuses each pair of cores into one “core”, halving the core count while doubling the number of threads per core. SMT4 variants are intended for PowerNV platforms running Linux, and SMT8 variants are intended for use with IBM's PowerVM hypervisor which can run Linux, AIX or IBM i.[1]
Markings
Part numbers for different POWER9 Sforza SKUs can be found on page 58 of the datasheet. These part numbers are printed on the surface of the CPU module and can be used to determine the type of the CPU.
Modules
| Chip | Module | Memory Channels | XBUS Lanes | PCIe Lanes | OpenCAPI Lanes | Socket |
|---|---|---|---|---|---|---|
| Nimbus | Sforza | 4 | 1 | 48 | 0 | LGA2601 |
| Monza | 8 | 1 | 34 | 48 | ? | |
| LaGrange | 8 | 2 | 42 | 16 | ? | |
| Cumulus | (unknown) | (memory attached via Centaurs) | (unknown) | (unknown) | (unknown) | ? |
| Axon | (unknown) | (unknown) | (unknown) | (unknown) | (unknown) | ? |
Nimbus
Nimbus chips are available in three different modules: Sforza, Monza, and LaGrange. Each module uses the same silicon mask but is packaged differently, exposing different I/O functionality to the host platform, allowing purpose-built systems to be constructed in addition to more general-purpose computers.
Sforza is the most flexible of these packages, providing PCIe 4.0 lanes as the main I/O resource, and is what Talos™ II uses for maximal similarity to existing desktop, workstation, and server systems.
Monza modules offer the most OpenCAPI/NVLink bandwidth and are used in IBM's AC922 (Witherspoon) systems, such as those used by the Sierra and Summit supercomputers.
LaGrange modules offer increased XBus bandwidth between processor sockets and are used by the Google/Rackspace Zaius motherboard used in the Barreleye G2 system.[2]
Cumulus
Little is known about Cumulus chips at this time; as Scale Up chips, they will trade some I/O bandwidth for support for more than two sockets.[3]
References
- ↑ Stuecheli, Jeff. POWER9. Presentation for AIX VUG. (video download, slides, timemarks)
- ↑ Gangidi, Adi Zaius/Barreleye G2 Server Development Update. 2017-11-13
- ↑ Morgan, Timothy Prickett. POWER9 to the People. 2017-12-05
Resources
- POWER9 CPU and Platform Documentation
- POWER9 Hardware Compatibility List
- Basic POWER9 overview presentation
- Power ISA version 3.0B - implemented by POWER9
