Difference between revisions of "PPC405"
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|title = Processor Information | |title = Processor Information | ||
|header1 = PowerPC 405 | |header1 = PowerPC 405 | ||
| − | |label2 = [[ | + | |label2 = [[Power ISA|Power ISA]] |
| − | |data2 = v2.03 ([[ | + | |data2 = v2.03 ([[Book_IIIE|Book III-E]]) |
|label3 = Process node | |label3 = Process node | ||
|data3 = Variable | |data3 = Variable | ||
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}} | }} | ||
| − | The PowerPC 405 is a long-lived embedded core, implementing the Power ISA v2.03 according to the Book III-E specification. It has seen use as an embedded controller in and around the POWER systems for quite some time, and is notable for being used to implement the [[POWER8|POWER8]] [[OCC|OCC]] functionality. | + | [[File:Ppc405_core.png|200px|thumb|right|PPC405 block diagram]]The PowerPC 405 is a long-lived embedded core, implementing the [[Power ISA|Power ISA]] v2.03 according to the [[Book_IIIE|Book III-E]] specification. It has seen use as an embedded controller in and around the POWER systems for quite some time, and is notable for being used to implement the [[POWER8|POWER8]] [[OCC|OCC]] functionality. |
== References == | == References == | ||
Latest revision as of 10:01, 12 February 2018
| PowerPC 405 | |
|---|---|
| Power ISA | v2.03 (Book III-E) |
| Process node | Variable |
| L1 cache | 16k data / 16k instruction |
The PowerPC 405 is a long-lived embedded core, implementing the Power ISA v2.03 according to the Book III-E specification. It has seen use as an embedded controller in and around the POWER systems for quite some time, and is notable for being used to implement the POWER8 OCC functionality.
