Difference between revisions of "Talk:OpenPOWER Firmware"
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<sub>[[User:AbstractConcept|AbstractConcept]] ([[User talk:AbstractConcept|talk]])</sub> 11:23, 30 June 2021 (CDT) | <sub>[[User:AbstractConcept|AbstractConcept]] ([[User talk:AbstractConcept|talk]])</sub> 11:23, 30 June 2021 (CDT) | ||
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| + | It is practically guaranteed that the CPU SEEPROM is a separate die to the main POWER9 die, probably attached via I2C. Consider [https://en.wikipedia.org/wiki/File:POWER8-DCM.jpg this photo] of a POWER8 module without the heatspreader, probably some of those additional chips are SEEPROMs. | ||
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| + | The BMC SPI flash is separate to the POWER firmware SPI flash; they are both in separate sockets on the mainboard. --[[User:HLandau|HLandau]] ([[User talk:HLandau|talk]]) 16:13, 20 July 2021 (CDT) | ||
Latest revision as of 16:13, 20 July 2021
Locations of SEEPROM and BMC SPI Flash
I can find this reference on IBM's site, https://developer.ibm.com/technologies/linux/articles/protect-system-firmware-openpower
The SBE has several stages, with the first part stored in processor one-time programmable read-only memory (OTPROM) and another part stored in the SEEPROM module located on the POWER processor module.
which suggests that SEEPROM is actually a tiny chip outside the POWER9?/POWER8? die, but I am not positive.
Also, this wiki page mentions "BMC SPI Flash", but I am unsure if this is a separate physical flash chip from PNOR?
AbstractConcept (talk) 11:23, 30 June 2021 (CDT)
It is practically guaranteed that the CPU SEEPROM is a separate die to the main POWER9 die, probably attached via I2C. Consider this photo of a POWER8 module without the heatspreader, probably some of those additional chips are SEEPROMs.
The BMC SPI flash is separate to the POWER firmware SPI flash; they are both in separate sockets on the mainboard. --HLandau (talk) 16:13, 20 July 2021 (CDT)
