Speculative Execution Vulnerabilities of 2018
In January of 2018, news of three speculative execution vulnerabilities was made public. Information about these vulnerabilities had been disclosed in private to certain companies and projects in June of 2016.
|CVE-2017-5715||Spectre||Variant 2||indirect branch prediction with side-channel analysis|
|CVE-2017-5753||Spectre||Variant 1||branch prediction with side-channel analysis|
|CVE-2017-5754||Meltdown||Variant 3||indirect branch prediction with side-channel analysis of data cache|
According to the official CVE list, this may affect processors using "speculative execution and indirect branch prediction". Google's Project Zero calls this Variant 2: branch target injection.
Hardware fixes are in place for POWER9 Nimbus DD2.2 / Cumulus DD1.1 and above . With these hardware changes, Spectre variant 2 is believed to be mitigated on the production POWER9 devices. Note that firmware applies the protections by throwing chicken switches in the silicon; as a result, the protection level is configurable via firmware flags.
According to the official CVE list, this may affect processors using "speculative execution and branch prediction". Google's Project Zero calls this Variant 1: bounds check bypass.
Hardware fixes are in place for POWER9 Nimbus DD2.2 / Cumulus DD1.1 and above . With these hardware changes, cross-process attacks via Spectre variant 1 are believed to be fully mitigated on the production POWER9 devices.
According to the official CVE list, this may affect processors using "speculative execution and indirect branch prediction", but specifically uses a data cache side channel. Google's Project Zero calls this Variant 3: rogue data cache load.
POWER7, POWER8, and POWER9 are patched from CVE-2017-5754 by purging the L1 cache when context switching to a less privileged process, as the vulnerability on these architectures affects L1 but not L2 cache. Firmware updates are also required to enable workarounds at the hardware level. .
Official statement from Raptor Computing Systems regarding Talos™ II
POWER9 will not ship with vulnerability to Meltdown or any loss in performance compared with the current prototype chips (DD2.1). Further, Spectre is fully mitigated with the exception of the same-process issue that is affecting the entire CPU industry. As far as we are aware there will be no further mitigation from any major CPU vendor now or in the future, as the remaining Spectre issue has been deemed an application level programming issue versus a CPU design issue. Patches for GCC to help fix the affected applications are already rolling out.
Attack surface reduction
Some known speculative execution vulnerabilities, e.g. MDS, rely on the CPU sharing some state between SMT threads running on the same core. In response, some operating systems (such as Kicksecure) have disabled SMT  in order to preemptively mitigate future speculative execution vulnerabilities. Given that POWER9 L2 and L3 cache is per-slice, not per-core , users who are disabling SMT and desire maximum protection from future speculative execution vulnerabilities may wish to only enable one core per slice. This is already the case for 4-core and 8-core CPU's sold by Raptor  Conversely, while disabling SMT and enabling only one core per slice is probably the most secure configuration, it is likely that enabling two cores per slice with SMT enabled will provide better security than one core per slice with SMT enabled, because doing so increases the amount of cache noise, making attacks more difficult. To summarize:
|Disabled||Unpaired||1 thread per cache (most secure, no shared state)||4 to 8 threads per CPU||Cheap|
|Disabled||Paired||2 threads per cache (least secure, SNR 1:0)||18 to 22 threads per CPU||Expensive|
|Enabled||Unpaired||4 threads per cache (relatively secure, SNR 1:2)||16 to 32 threads per CPU||Cheap|
|Enabled||Paired||8 threads per cache (very secure, SNR 1:6)||72 to 88 threads per CPU||Expensive|
To date, researchers have not successfully demonstrated attacks against 4 or 8 threads per cache. Whether this is because such attacks are too difficult to achieve or simply because they are inapplicable to x86 CPU's (where most of the research funding lives) remains to be seen.
- Reading privileged memory with a side-channel. Google Project Zero blog
- CVE-2017-5715. Mitre CVE List. "Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis."
- CVE-2017-5753. Mitre CVE List. "Systems with microprocessors utilizing speculative execution and branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis."
- CVE-2017-5754. Mitre CVE List. "Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis of the data cache."
- IBM PSIRT Blog post, Potential Impact on Processors in the POWER family
- TenFourFox Development blog post, Actual field testing of Spectre on various Power Macs
- Raptor Engineering GNU Social notices about POWER8 and POWER9 vulnerability
- Red Hat security page for Kernel Side-Channel Attacks
- Hostboot commit message listing security changes for NDD2.2 / CDD1.1
- Larabel, Michael. PowerPC Memory Protection Keys In For Linux 4.16, Power Has Meltdown Mitigation In 4.15. 2018-01-22
- IBM Power8 Systems Server Firmware
- IBM POWER9 Systems Server Firmware
- IBM Addresses Reported Intel Security Vulnerabilities
- Whonix 15 Security Enhancements
- Kicksecure Packages for Debian Hosts
- security-misc Boot parameters