Power ISA/Machine State Register

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Revision as of 13:20, 20 January 2018 by Torpcoms (talk | contribs) (add III-S info)
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Machine State Register
Bit Code Name Defined
2.07 3.0B
0 SF Sixty-Four-Bit Mode Yes Yes
1:2 Reserved No No
3 HV Hypervisor State Yes Yes
4 Reserved No No
5 SLE Split Little Endian Yes Yes[note 1]
6:28 Reserved No No
29:30 TS Transaction State Yes Yes
31 TM Transactional Memory Available Yes Yes
32:37 Reserved No No
38 VEC Vector Available Yes Yes
39 Reserved No No
40 VSX VSX Available Yes Yes
41:47 Reserved No No
48 EE External Interrupt Enable Yes Yes
49 PR Problem State Yes Yes
50 FP Floating-Point Available Yes Yes
51 ME Machine Check Interrupt Enable Yes Yes
52 FE0 Floating-Point Exception Mode 0 Yes Yes
53 SE Single-Step Trace Enable Yes Yes[note 2]
54 BE Branch Trace Enable Yes Yes[note 2]
55 FE1 Floating-Point Exception Mode 1 Yes Yes
56:57 Reserved No No
58 IR Instruction Relocate Yes Yes
59 DR Data Relocate Yes Yes
60 Reserved No No
61 PMM Performance Monitor Mark Yes Yes
62 RI Recoverable Interrupt Yes Yes
63 LE Little-Endian Mode Yes Yes
  1. Power version ISA 3.0B defines this bit as something set in hardware to be zero, and warns against changing it.
  2. 2.0 2.1 Power ISA version 3.0B defines bits 53 and 54 together as TE - Trace Enable - and defines having both bits set as reserved