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Package Information
Processor POWER9
Chip Nimbus
Maximum base clock -
Maximum WOF clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 4
Maximum PCIe lanes 42
Maximum PCIe endpoints -
CAPI 2.0 interfaces -
OpenCAPI/NVLink lanes 16
OpenCAPI interfaces 2
NVLink interfaces 1

For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see Nimbus.

LaGrange is the codename for a POWER9, Nimbus chip, CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the Sforza module, and the maximum OpenCAPI/NVLink connectivity of the Monza module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules.

LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board.

LaGrange will be used for the upcoming RCS Condor board, albeit in a single-socket configuration.

Known Nimbus-LaGrange parts
Part Cores Stepping Nest/Boost/Base (GHz) Max
02CY069 22 DD2.2 2.00/3.80/2.90 225 W
02CY574 DD2.3
02CY254 20 DD2.2 2.00/3.80/2.90 225 W
02CY582 DD2.3
02CY249 16 DD2.2 2.00/3.90/3.40 225 W
02CY584 DD2.3 2.00/4.00/3.35
02AA947 DD2.1 2.00/3.80/2.95
02CY057 18 DD2.2 2.00/3.80/2.80 190 W
02CY575 DD2.3
02WP188 12 DD2.3 2.00/3.80/2.80 160 W

Sourced from LaGrange data sheet v1.7 (see Table 6-10 on page 66) and LaGrange data sheet v1.8 (see Table 6-10 on page 66).

See Also

External Links