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Low Pin Count (LPC): Refers to the Low Pin Count interface of the platform. LPC is a derivative of ISA, designed to use the ISA protocol over fewer physical wires.

Description of the POWER LPC interface from a kernel commit message -+

The LPC (Low Pin Count) interface on a POWER8 is made accessible to the system through the ADU (XSCOM interface). This interface is part of set of units connected together via a local OPB (On-Chip Peripheral Bus) which act as a bridge between the ADU and the off chip LPC endpoints, like external flash modules.

The most important units of this OPB are :

- OPB Master: contains the ADU slave logic, a set of internal
  registers and the logic to control the OPB.
- LPCHC (LPC HOST Controller): which implements a OPB Slave, a set of
  internal registers and the LPC HOST Controller to control the LPC

Four address spaces are provided to the ADU :

- LPC Bus Firmware Memory
- LPC Bus Memory
- LPC Bus I/O (ISA bus)
- and the registers for the OPB Master and the LPC Host Controller

On POWER8, an intermediate hop is necessary to reach the OPB, through a unit called the ECCB. OPB commands are simply mangled in ECCB write commands.

On POWER9, the OPB master address space can be accessed via MMIO. The logic is same but the code will be simpler as the XSCOM and ECCB hops are not necessary anymore.