Difference between revisions of "Coreboot/ToDo"

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** DDR4 training(!)
** DDR4 training(!)
* Get ramstage up and running
* Get ramstage up and running
** PCIe setup
** Power management setup / OCC start
** Handoff to skiboot
** Handoff to skiboot
=== Resources ===
=== Resources ===
* [[:Category:Documentation|Online Documentation]]
* [[:Category:Documentation|Online Documentation]]

Latest revision as of 20:15, 22 January 2019

Coreboot for POWER9


  • Replace hostboot
  • Speed up IPL
  • Migrate from tangle of FSP routines to clean coreboot codebase
  • Get simulator up and running for early POWER9 init -- qemu?
  •  ???


Roughly in logical order

  • Update coreboot toolchain for POWER9
  • Document
    • Exactly what coreboot needs to do in terms of hardware configuration
    • What state the processor is in at entry to coreboot (exit from SBE)
    • What state the processor needs to be left in at exit from coreboot (entry to skiboot)
  • Determine extent of existing POWER9 emulation in coreboot
    • skiboot and skiroot are believed to work in the simulation environment
    • The hardware underlying hostboot is mostly un-emulated, though very basic ppc64 software remains able to be executed. May be enough to debug bootblock / exit from SBE?
  • Determine if simulation or direct hardware development is going to be the better route
  • Replace HBBL with coreboot bootblock
    • Load and cryptographically verify romstage
  • Get romstage up and running
    • Nest start
    • Fabric setup
    • XBUS training / configuration
    • SMP init
    • DDR4 training(!)
  • Get ramstage up and running
    • Handoff to skiboot