Power ISA/Privilege States

States

Ultravisor State

At the moment very little information exists about the Ultravisor State. It is not mentioned in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible privilege of instructions. There is no official documentation of a UV - Ultravisor State Machine State Register bit, although some source code does reference its existence.

A report from IBM for the Air Force Research Laboratory indicates than Ultravisor State was tested in a modified POWER8 processor simulation. It is currently unknown if which, if any, POWER9 processors are capable of Ultravisor State

Hypervisor State

Hypervisor State was introduced in POWER4, although for some time it was not included in documentation, appearing only as a reserved bit in the Machine State Register. It is indicated by the HV (bit 3) of the Machine State Register

Privileged State

Also called Supervisor Mode

Problem State

Also called User Mode

Instruction Classification

Privilege Classification of Instructions in Power ISA

Code	2.07	3.0B	Description
P	Yes	Yes	a privileged instruction.
O	Yes	Yes	an instruction that is treated as privileged or nonprivileged (or hypervisor, for mtspr), depend- ing on the SPR or PMR number.
PI	No	Yes	an instruction that is illegal in privileged state.
H	Yes	Yes	an instruction that can be executed only in hypervisor state
PH	Yes	No	a hypervisor privileged instruction if Category Embedded.Hypervisor is implemented; otherwise denotes a privileged instruction.
M	Yes	No	an instruction that is treated as privileged or nonprivileged, depending on the value of the UCLE bit in the MSR
U	No	Yes	an instruction that can be executed only in ultravisor state