Power ISA/Machine State Register

Machine State Register

Bit	Code	Name	Defined
			2.07		3.0B
			III-S	III-E
0	SF	Sixty-Four-Bit Mode	Yes	No	Yes
1:2	Reserved		No	No	No
3	HV	Hypervisor State	Yes	No	Yes
4	Reserved		No	No	No
5	SLE	Split Little Endian	Yes	No	Yes
6:28	Reserved		No	No	No
29:30	TS	Transaction State	Yes	No	Yes
31	TM	Transactional Memory Available	Yes	No	Yes
32	CM	Computation Mode	No	Yes	No
33	Reserved		No	No	No
34	Implementation-dependant		No	Yes	No
35	GS	Guest State	No	Yes	No
36	Implementation-dependant		No	Yes	No
37	UCLE	User Cache Locking Enable	No	Yes	No
38	VEC	Vector Available	Yes	Yes	Yes
39	Reserved		No	No	No
40	VSX	VSX Available	Yes	Yes	Yes
41:45	Reserved		No	No	No
46	CE	Critical Enable	No	Yes	No
47	Reserved		No	No	No
48	EE	External Interrupt Enable	Yes	Yes	Yes
49	PR	Problem State	Yes	Yes	Yes
50	FP	Floating-Point Available	Yes	Yes	Yes
51	ME	Machine Check Interrupt Enable	Yes	Yes	Yes
52	FE0	Floating-Point Exception Mode 0	Yes	Yes	Yes
53	SE	Single-Step Trace Enable	Yes	Yes	Yes
54	BE	Branch Trace Enable	Yes	Yes	Yes
55	FE1	Floating-Point Exception Mode 1	Yes	Yes	Yes
56	Reserved		No	No	No
57	Reserved		No	No	No
58	IR	Instruction Relocate	Yes	Yes	Yes
59	DR	Data Relocate	Yes	Yes	Yes
60		Implementation-dependant	No	Yes	No
61	PMM	Performance Monitor Mark	Yes	Yes	Yes
62	RI	Recoverable Interrupt	Yes	No	Yes
63	LE	Little-Endian Mode	Yes	No	Yes