LaGrange

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Revision as of 09:57, 29 December 2017 by Torpcoms (talk | contribs) (add nimbus chip)

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Package Information
LaGrange
Processor	POWER9
Chip	Nimbus
Maximum base clock	-
Maximum WOF clock	-
Maximum TDP	-
PCIe controllers (PEC)	-
PCIe generation	4
Maximum PCIe lanes	42
Maximum PCIe endpoints	-
CAPI 2.0 interfaces	-
OpenCAPI interfaces	-
NVLink interfaces	-

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Nimbus Modules