LaGrange
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Package Information
LaGrange
Processor
POWER9
Chip
Nimbus
Maximum base clock
-
Maximum
WOF
clock
-
Maximum
TDP
-
PCIe controllers (
PEC
)
-
PCIe generation
4
Maximum PCIe lanes
42
Maximum PCIe endpoints
-
CAPI 2.0
interfaces
-
OpenCAPI
/
NVLink
lanes
16
OpenCAPI
interfaces
2
NVLink
interfaces
1
External Links
LaGrange Module at IBM OpenPOWER portal
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