OpenPOWER Firmware

OpenPOWER Firmware is an open-source alternative to OpenFirmware and proprietary IBM firmware used on Power machines. It is a general name for many separate pieces of software used to start recent Power Architecture chips made by IBM.

OpenBMC is a separate project that creates firmware for the Baseboard Management Controller.

Components

Firmware	Executed on	Loaded from	Function
OTPROM	SBE core (on CPU chip)	eFuses Source	very first instructions executed loads SBE firmware from SEEPROM into SBE core
Self-Boot Engine (SBE) firmware	SBE core (on CPU chip)	SBE SEEPROM Source	initialises CPU core loads Hostboot Bootloader backup copy stored on PNOR SPI Flash, used to stage SBE firmware updates
Hostboot Bootloader (HBBL)	CPU core	SBE SEEPROM Source	first code which runs on main CPU cores; loads and executes rest of Hostboot responsible for verifying integrity of Hostboot when secure boot is enabled, so this part of Hostboot is stored on the SBE SEEPROM, even though its source code lives inside the Hostboot repository
Hostboot	CPU core	PNOR SPI Flash Source	initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers finally, chainloads Skiboot
Skiboot	CPU core	PNOR SPI Flash Source	initialises PCIe controllers, device trees, real time clock, NVlink, sensors loads OCC firmware and starts OCC running implements OpenPOWER Abstraction Layer (OPAL) for OS runtime services; remains resident in RAM after OS boot finally, chainloads Skiroot
Skiroot/Petitboot	CPU core	PNOR SPI Flash Source	Skiroot refers to the Linux kernel and initramfs which runs from RAM Contains Petitboot, a userspace application which provides a boot menu Petitboot loads operating system via kexec
On-Chip Controller (OCC) firmware	OCC core (on CPU chip)	PNOR SPI Flash Source	thermal regulation of CPU chip, turbo frequency selection, voltage ID selection, power measurement, etc.
CME HCODE	CME cores (on CPU chip)	PNOR SPI Flash Source	The Core Management Engines are auxillary cores used for power management purposes. They are ultimately responsible to the OCC. There is one CME for every two SMT4 cores.
SGPE and PGPE HCODE	General Purpose Engine cores (on CPU chip)	PNOR SPI Flash Source	Auxillary cores which assist, and are managed by, the OCC. The Stop GPEs (SGPEs) are part of the mechanism for resuming execution after a STOP instruction is executed (which is a Power ISA instruction which halts the processor). The Pstate GPEs (PGPEs) perform pstate management.
IOPPE HCODE	IOPPE cores (on CPU chip)	PNOR SPI Flash Source	Involved in CAPI support.
OpenBMC	BMC chip	BMC SPI Flash Source	(This is not part of OpenPOWER firmware, but is mentioned to give a picture of the division of responsibilities. Not all POWER9 systems use a BMC; IBM systems use a FSP.) Turns system power rails on and off to energise and deenergise CPU modules, RAM, etc. Sends commands to CPU modules over FSI to commence booting. Provides access to PNOR SPI flash containing host firmware via LPC. Receives core temperature information from the OCC; decides and sets fan speeds. Powers off system if OCC indicates catastrophic temperature.

Diagram of main and auxillary cores on POWER9

Process

1. SBE executes OTPROM, which loads SEEPROM firmware into SBE PIBMEM
2. SBE executes SEEPROM firmware
3. OpenBMC uses FSI interface to start SBE
4. SBE loads Hostboot
5. Hostboot loads Skiboot
6. Skiboot loads OCC, Skiroot
7. Petitboot application within Skiroot loads the operating system
8. OS talks to firmware through OPAL

See also

• OpenBMC
• OpenPOWER

External Links

• OpenPOWER firmware source code on GitHub
• For a better understanding of OpenPOWER firmware and boot processes, see:
  • Overview of Boot Process
  • P9 Boot Flow
  • More OpenPOWER firmware documentation
  • OpenPOWER Firmware Stack - Joel's Weblog
• Bug tracker for firmware issues specific to Raptor CS products: https://bugs.raptorengineering.com/