Difference between revisions of "Coreboot/ToDo"
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(Created page with "== Coreboot for POWER9 == === Goals === * Replace hostboot * Speed up IPL * Migrate from tangle of FSP routines to clean coreboot codebase * Get simulator up and running for...") |
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** Nest start | ** Nest start | ||
** Fabric setup | ** Fabric setup | ||
| + | ** XBUS training / configuration | ||
** SMP init | ** SMP init | ||
| + | ** DDR4 training(!) | ||
* Get ramstage up and running | * Get ramstage up and running | ||
| − | |||
** PCIe setup | ** PCIe setup | ||
| + | ** Power management setup / OCC start | ||
** Handoff to skiboot | ** Handoff to skiboot | ||
Revision as of 06:08, 3 May 2018
Coreboot for POWER9
Goals
- Replace hostboot
- Speed up IPL
- Migrate from tangle of FSP routines to clean coreboot codebase
- Get simulator up and running for early POWER9 init -- qemu?
- ???
Tasks
Roughly in logical order
- Update coreboot toolchain for POWER9
- Document
- Exactly what coreboot needs to do in terms of hardware configuration
- What state the processor is in at entry to coreboot (exit from SBE)
- What state the processor needs to be left in at exit from coreboot (entry to skiboot)
- Determine extent of existing POWER9 emulation in coreboot
- skiboot and skiroot are believed to work in the simulation environment
- The hardware underlying hostboot is mostly un-emulated, though very basic ppc64 software remains able to be executed. May be enough to debug bootblock / exit from SBE?
- Determine if simulation or direct hardware development is going to be the better route
- Get romstage up and running
- Nest start
- Fabric setup
- XBUS training / configuration
- SMP init
- DDR4 training(!)
- Get ramstage up and running
- PCIe setup
- Power management setup / OCC start
- Handoff to skiboot
