Difference between revisions of "Power ISA/Machine State Register"

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(add III-S info)
(add III-E info)
Line 16: Line 16:
 
|Sixty-Four-Bit Mode
 
|Sixty-Four-Bit Mode
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
 
!1:2
 
!1:2
−
|
+
|colspan="2"|Reserved
−
|Reserved
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
 
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 30: Line 29:
 
|Hypervisor State
 
|Hypervisor State
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
 
!4
 
!4
−
|
+
|colspan="2"|Reserved
−
|Reserved
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
 
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 44: Line 42:
 
|Split Little Endian
 
|Split Little Endian
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|style="background:#FF9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power version ISA 3.0B defines this bit as something set in hardware to be zero, and warns against changing it.</ref>
+
|style="background:#FF9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 3.0B defines this bit as something set in hardware to be zero, and warns against changing it.</ref>
 
|-
 
|-
 
!6:28
 
!6:28
−
|
+
|colspan="2"|Reserved
−
|Reserved
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
 
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 58: Line 55:
 
|Transaction State
 
|Transaction State
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 65: Line 62:
 
|Transactional Memory Available
 
|Transactional Memory Available
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 +
|-
 +
!32
 +
|CM
 +
|Computation Mode
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|-
 +
!33
 +
|colspan="2"|Reserved
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|-
 +
!34
 +
|colspan="2"|Implementation-dependant
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#99F;vertical-align:middle;text-align:center;"|Yes
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|-
 +
!35
 +
|GS
 +
|Guest State
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
−
!32:37
+
!36
−
|
+
|colspan="2"|Implementation-dependant
−
|Reserved
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#99F;vertical-align:middle;text-align:center;"|Yes
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|-
 +
!37
 +
|UCLE
 +
|User Cache Locking Enable
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 79: Line 108:
 
|Vector Available
 
|Vector Available
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#FF9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 2.07 Book III-E defines this as ''SPV'' - ''SP/Embedded Floating-Point/Vector Available''</ref>
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
 
!39
 
!39
−
|
+
|colspan="2"|Reserved
−
|Reserved
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
 
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 93: Line 121:
 
|VSX Available
 
|VSX Available
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
 
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 +
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 +
|-
 +
!41:45
 +
|colspan="2"|Reserved
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|-
 +
!46
 +
|CE
 +
|Critical Enable
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
−
!41:47
+
!47
−
|
+
|colspan="2"|Reserved
−
|Reserved
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
 
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 107: Line 147:
 
|External Interrupt Enable
 
|External Interrupt Enable
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 2.07 Book III-E calls this ''External Enable''</ref>
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 114: Line 154:
 
|Problem State
 
|Problem State
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 121: Line 161:
 
|Floating-Point Available
 
|Floating-Point Available
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 128: Line 168:
 
|Machine Check Interrupt Enable
 
|Machine Check Interrupt Enable
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 2.07 Book III-E calls this ''Machine Check Enable''</ref>
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 135: Line 175:
 
|Floating-Point Exception Mode 0
 
|Floating-Point Exception Mode 0
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 142: Line 182:
 
|Single-Step Trace Enable
 
|Single-Step Trace Enable
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#99F;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 2.07 Book III-E defines this as Implementation-dependent</ref>
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note" name="msr_te">Power ISA version 3.0B defines bits 53 and 54 together as ''TE'' - Trace Enable - and defines having both bits set as ''reserved''</ref>
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note" name="msr_te">Power ISA version 3.0B defines bits 53 and 54 together as ''TE'' - ''Trace Enable'' - and defines having both bits set as ''reserved''</ref>
 
|-
 
|-
 
!54
 
!54
Line 149: Line 189:
 
|Branch Trace Enable
 
|Branch Trace Enable
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#FF9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 2.07 Book III-E defines this as ''DE'' - ''Debug Interrupt Enable''</ref>
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note" name="msr_te"/>
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note" name="msr_te"/>
 
|-
 
|-
Line 156: Line 196:
 
|Floating-Point Exception Mode 1
 
|Floating-Point Exception Mode 1
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
−
!56:57
+
!56
−
|
+
|colspan="2"|Reserved
−
|Reserved
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 +
|-
 +
!57
 +
|colspan="2"|Reserved
 +
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
 
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 170: Line 215:
 
|Instruction Relocate
 
|Instruction Relocate
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#FF9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 2.07 Book III-E defines this as ''IS'' - ''Instruction Address Space''</ref>
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 177: Line 222:
 
|Data Relocate
 
|Data Relocate
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#FF9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power ISA version 2.07 Book III-E defines this as ''DS'' - ''Data Address Space''</ref>
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
 
!60
 
!60
 
|
 
|
−
|Reserved
+
|Implementation-dependant
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
−
|
+
|style="background:#99F;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|-
 
|-
Line 191: Line 236:
 
|Performance Monitor Mark
 
|Performance Monitor Mark
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 198: Line 243:
 
|Recoverable Interrupt
 
|Recoverable Interrupt
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|-
 
|-
Line 205: Line 250:
 
|Little-Endian Mode
 
|Little-Endian Mode
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
−
|
+
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
|}
 
|}
  
 
<references group="note"/>
 
<references group="note"/>

Revision as of 14:14, 20 January 2018

Machine State Register
Bit Code Name Defined
2.07 3.0B
III-S III-E
0 SF Sixty-Four-Bit Mode Yes No Yes
1:2 Reserved No No No
3 HV Hypervisor State Yes No Yes
4 Reserved No No No
5 SLE Split Little Endian Yes No Yes[note 1]
6:28 Reserved No No No
29:30 TS Transaction State Yes No Yes
31 TM Transactional Memory Available Yes No Yes
32 CM Computation Mode No Yes No
33 Reserved No No No
34 Implementation-dependant No Yes No
35 GS Guest State No Yes No
36 Implementation-dependant No Yes No
37 UCLE User Cache Locking Enable No Yes No
38 VEC Vector Available Yes Yes[note 2] Yes
39 Reserved No No No
40 VSX VSX Available Yes Yes Yes
41:45 Reserved No No No
46 CE Critical Enable No Yes No
47 Reserved No No No
48 EE External Interrupt Enable Yes Yes[note 3] Yes
49 PR Problem State Yes Yes Yes
50 FP Floating-Point Available Yes Yes Yes
51 ME Machine Check Interrupt Enable Yes Yes[note 4] Yes
52 FE0 Floating-Point Exception Mode 0 Yes Yes Yes
53 SE Single-Step Trace Enable Yes Yes[note 5] Yes[note 6]
54 BE Branch Trace Enable Yes Yes[note 7] Yes[note 6]
55 FE1 Floating-Point Exception Mode 1 Yes Yes Yes
56 Reserved No No No
57 Reserved No No No
58 IR Instruction Relocate Yes Yes[note 8] Yes
59 DR Data Relocate Yes Yes[note 9] Yes
60 Implementation-dependant No Yes No
61 PMM Performance Monitor Mark Yes Yes Yes
62 RI Recoverable Interrupt Yes No Yes
63 LE Little-Endian Mode Yes No Yes
  1. ↑ Power ISA version 3.0B defines this bit as something set in hardware to be zero, and warns against changing it.
  2. ↑ Power ISA version 2.07 Book III-E defines this as SPV - SP/Embedded Floating-Point/Vector Available
  3. ↑ Power ISA version 2.07 Book III-E calls this External Enable
  4. ↑ Power ISA version 2.07 Book III-E calls this Machine Check Enable
  5. ↑ Power ISA version 2.07 Book III-E defines this as Implementation-dependent
  6. ↑ 6.0 6.1 Power ISA version 3.0B defines bits 53 and 54 together as TE - Trace Enable - and defines having both bits set as reserved
  7. ↑ Power ISA version 2.07 Book III-E defines this as DE - Debug Interrupt Enable
  8. ↑ Power ISA version 2.07 Book III-E defines this as IS - Instruction Address Space
  9. ↑ Power ISA version 2.07 Book III-E defines this as DS - Data Address Space
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