Difference between revisions of "Sforza"
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(add nimbus chip) |
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|label2 = Processor | |label2 = Processor | ||
|data2 = [[POWER9|POWER9]] | |data2 = [[POWER9|POWER9]] | ||
| − | |label3 = Maximum base clock | + | |label3 = Chip |
| − | | | + | |data3 = Nimbus |
| − | | | + | |label4 = Maximum base clock |
| − | | | + | |data4 = 3.1GHz (4/8 core) |
| − | | | + | |label5 = Maximum [[WOF|WOF]] clock |
| − | | | + | |data5 = 3.8GHz (4/8 core) |
| − | | | + | |label6 = Maximum [[TDP|TDP]] |
| − | | | + | |data6 = 190W |
| − | | | + | |label7 = PCIe controllers ([[PEC|PEC]]) |
| − | | | + | |data7 = 3 |
| − | | | + | |label8 = PCIe generation |
| − | | | + | |data8 = 4 |
| − | | | + | |label9 = Maximum PCIe lanes |
| − | | | + | |data9 = 48 |
| − | | | + | |label10 = Maximum PCIe endpoints |
| − | | | + | |data10 = 6 |
| − | | | + | |label11 = [[CAPI 2.0|CAPI 2.0]] interfaces |
| − | + | |data11 = 2 | |
| − | + | |label12 = [[OpenCAPI|OpenCAPI]] interfaces | |
|data12 = 0 | |data12 = 0 | ||
| + | |label13 = [[NVLink|NVLink]] interfaces | ||
| + | |data13 = 0 | ||
}} | }} | ||
Revision as of 09:48, 29 December 2017
| Sforza | |
|---|---|
| Processor | POWER9 |
| Chip | Nimbus |
| Maximum base clock | 3.1GHz (4/8 core) |
| Maximum WOF clock | 3.8GHz (4/8 core) |
| Maximum TDP | 190W |
| PCIe controllers (PEC) | 3 |
| PCIe generation | 4 |
| Maximum PCIe lanes | 48 |
| Maximum PCIe endpoints | 6 |
| CAPI 2.0 interfaces | 2 |
| OpenCAPI interfaces | 0 |
| NVLink interfaces | 0 |
Sforza is the codename for the POWER9 SO CPU package used by the Talos™ II systems. It focuses on general purpose computing, with high I/O available over standard PCIe generation 4 interfaces.
