Difference between revisions of "Power ISA/Privilege States"
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=== Ultravisor State === | === Ultravisor State === | ||
| − | At the moment very little information exists about the Ultravisor State. It is not mentioned in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible privilege of instructions. There is no official documentation of a ''UV'' - ''Ultravisor State'' [[Machine State Register]] bit, although some source code does reference its existence.<ref>https://patchwork.ozlabs.org/patch/719952/</ref> | + | At the moment very little information exists about the Ultravisor State. It is not mentioned in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible privilege of instructions. There is no official documentation of a ''UV'' - ''Ultravisor State'' [[Machine State Register]] bit, although some source code does reference its existence.<ref>https://patchwork.ozlabs.org/patch/719952/</ref><ref>[https://www.ibm.com/developerworks/community/forums/atom/download/skiboot.pdf?nodeId=7d69546b-3d92-4320-8ed2-0ea61ab69d66 skiboot Documentation] Release v5.9</ref><ref>[[File:AFRL-RI-RS-TR-2017-021.pdf|HARDWARE SUPPORT FOR MALWARE DEFENSE AND END-TO-END TRUST]]. IBM. 2017-02</ref> |
=== Hypervisor State === | === Hypervisor State === | ||
Revision as of 02:10, 21 January 2018
Contents
States
Ultravisor State
At the moment very little information exists about the Ultravisor State. It is not mentioned in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible privilege of instructions. There is no official documentation of a UV - Ultravisor State Machine State Register bit, although some source code does reference its existence.[1][2][3]
Hypervisor State
Hypervisor State was introduced in POWER4, although for some time it was not included in documentation, appearing only as a reserved bit in the Machine State Register.[4] It is indicated by the HV (bit 3) of the Machine State Register
Privileged State
Also called Supervisor Mode
Problem State
Also called User Mode
Instruction Classification
| Code | 2.07 | 3.0B | Description |
|---|---|---|---|
| P | Yes | Yes | a privileged instruction. |
| O | Yes | Yes | an instruction that is treated as privileged or nonprivileged (or hypervisor, for mtspr), depend-
ing on the SPR or PMR number. |
| PI | No | Yes | an instruction that is illegal in privileged state. |
| H | Yes | Yes | an instruction that can be executed only in hypervisor state |
| PH | Yes | No | a hypervisor privileged instruction if Category Embedded.Hypervisor is implemented; otherwise
denotes a privileged instruction. |
| M | Yes | No | an instruction that is treated as privileged or nonprivileged, depending on the value of the UCLE
bit in the MSR |
| U | No | Yes | an instruction that can be executed only in ultravisor state |
References
- ↑ https://patchwork.ozlabs.org/patch/719952/
- ↑ skiboot Documentation Release v5.9
- ↑ File:AFRL-RI-RS-TR-2017-021.pdf. IBM. 2017-02
- ↑ Kerr, Jeremy. OpenPOWER: building an open-source software stack from bare metal (video). Linux.conf.au 2015
