Difference between revisions of "Power ISA/Machine State Register"
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m (Torpcoms moved page MSR to Machine State Register: Wiki pages here use full names) |
Revision as of 11:36, 20 January 2018
Bit | Code | Name |
---|---|---|
0 | SF | Sixty-Four-Bit Mode |
1:2 | Reserved | |
3 | HV | Hypervisor State |
4 | Reserved | |
5 | always zero | |
6:28 | Reserved | |
29:30 | TS | Transaction State |
31 | TM | Transactional Memory Available |
32:37 | Reserved | |
38 | VEC | Vector Available |
39 | Reserved | |
40 | VSX | VSX Available |
41:47 | Reserved | |
48 | EE | External Interrupt Enable |
49 | PR | Problem State |
50 | FP | Floating-Point Available |
51 | ME | Machine Check Interrupt Enable |
52 | FE0 | Floating-Point Exception Mode 0 |
53:54 | TE | Trace Enable |
55 | FE1 | Floating-Point Exception Mode 1 |
56:57 | Reserved | |
58 | IR | Instruction Relocate |
59 | DR | Data Relocate |
60 | Reserved | |
61 | PMM | Performance Monitor Mark |
62 | RI | Recoverable Interrupt |
63 | LE | Little-Endian Mode |