Difference between revisions of "LaGrange"
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JeremyRand (talk | contribs) (Link to POWER9) |
JeremyRand (talk | contribs) (Link to Nimbus) |
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|data2 = [[POWER9|POWER9]] | |data2 = [[POWER9|POWER9]] | ||
|label3 = Chip | |label3 = Chip | ||
| − | |data3 = Nimbus | + | |data3 = [[Nimbus]] |
|label4 = Maximum base clock | |label4 = Maximum base clock | ||
|data4 = - | |data4 = - | ||
Revision as of 16:12, 5 September 2022
| LaGrange | |
|---|---|
| Processor | POWER9 |
| Chip | Nimbus |
| Maximum base clock | - |
| Maximum WOF clock | - |
| Maximum TDP | - |
| PCIe controllers (PEC) | - |
| PCIe generation | 4 |
| Maximum PCIe lanes | 42 |
| Maximum PCIe endpoints | - |
| CAPI 2.0 interfaces | - |
| OpenCAPI/NVLink lanes | 16 |
| OpenCAPI interfaces | 2 |
| NVLink interfaces | 1 |
LaGrange is the codename for a POWER9 CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the Sforza module, and the maximum OpenCAPI/NVLink connectivity of the Monza module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules.
LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board.
LaGrange will be used for the upcoming RCS Condor board, albeit in a single-socket configuration.
| Part | Cores | Stepping | Nest/Boost/Base (GHz) | Max |
|---|---|---|---|---|
| 02CY069 | 22 | 2.00/3.80/2.90 | 225 W | |
| 02CY254 | 20 | 2.00/3.80/2.90 | 225 W | |
| 02CY249 | 16 | 2.00/3.80/3.40 | 225 W | |
| 02CY057 | 18 | 2.00/3.80/2.80 | 190 W |
Sourced from LaGrange data sheet (see Table 6-10 on page 66 in version 1.7)
