Difference between revisions of "Sforza"
Jump to navigation
Jump to search
(add nimbus chip) |
(rewriting to emphasise module/package characteristics, while also mentioning common features due to Nimbus chip type (SMT4/SO)) |
||
| Line 28: | Line 28: | ||
}} | }} | ||
| − | Sforza is the codename for | + | Sforza is the codename for a [[POWER9|POWER9]], [[Nimbus|Nimbus]] chip, CPU module/package designed for general purpose computing, with high I/O available over standard PCIe generation 4 interfaces. The Nimbus chip it houses has 24 cores on the die, each capable of SMT4, and as a [[Scale Out]] processor intended for dual socket systems, uses directly attached RAM. |
| + | |||
| + | It is used by the [[Talos_II|Talos™ II]] systems. | ||
[[Category:Nimbus Modules]] | [[Category:Nimbus Modules]] | ||
[[Category:Talos II Components]] | [[Category:Talos II Components]] | ||
Revision as of 13:58, 29 December 2017
| Sforza | |
|---|---|
| Processor | POWER9 |
| Chip | Nimbus |
| Maximum base clock | 3.1GHz (4/8 core) |
| Maximum WOF clock | 3.8GHz (4/8 core) |
| Maximum TDP | 190W |
| PCIe controllers (PEC) | 3 |
| PCIe generation | 4 |
| Maximum PCIe lanes | 48 |
| Maximum PCIe endpoints | 6 |
| CAPI 2.0 interfaces | 2 |
| OpenCAPI interfaces | 0 |
| NVLink interfaces | 0 |
Sforza is the codename for a POWER9, Nimbus chip, CPU module/package designed for general purpose computing, with high I/O available over standard PCIe generation 4 interfaces. The Nimbus chip it houses has 24 cores on the die, each capable of SMT4, and as a Scale Out processor intended for dual socket systems, uses directly attached RAM.
It is used by the Talos™ II systems.
