Difference between revisions of "Sforza"
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* [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_Sforza Sforza Module at IBM OpenPOWER portal] | * [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_Sforza Sforza Module at IBM OpenPOWER portal] | ||
| + | * [https://en.wikichip.org/wiki/ibm/cores/sforza WikiChip page for Sforza] | ||
[[Category:Modules]] | [[Category:Modules]] | ||
[[Category:POWER9]] | [[Category:POWER9]] | ||
[[Category:Mainboard Components]] | [[Category:Mainboard Components]] | ||
Revision as of 14:39, 5 April 2020
| Sforza | |
|---|---|
| Processor | POWER9 |
| Chip | Nimbus |
| Maximum base clock | 3.1GHz (4/8 core) |
| Maximum WOF clock | 3.8GHz (4/8 core) |
| Maximum TDP | 190W |
| PCIe controllers (PEC) | 3 |
| PCIe generation | 4 |
| Maximum PCIe lanes | 48 |
| Maximum PCIe endpoints | 6 |
| CAPI 2.0 interfaces | 2 |
| OpenCAPI interfaces | 0 |
| NVLink interfaces | 0 |
For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see Nimbus.
Sforza is the codename for a POWER9, Nimbus chip, CPU module/package designed for general purpose computing, with high I/O available over standard PCIe generation 4 interfaces. The Nimbus chip it houses has 24 cores on the die, each capable of SMT4, and as a Scale Out processor intended for dual socket systems, uses directly attached RAM.
It is used by the Talos™ II systems.
RCS modules sold
| Part | SKU | Name | Cores | Stepping |
|---|---|---|---|---|
| 02CY297? | CP9M01 | IBM POWER9 CPU (4-Core) | 4 | DD2.2 |
| 02CY089?? | CP9M02 | IBM POWER9 CPU (8-Core) | 8 | DD2.2 |
| 02CY489? | CP9M06 | IBM POWER9 CPU (18-Core) | 18 | DD2.2 |
| 02CY296? | CP9M08 | IBM POWER9 CPU (22-Core) | 22 | DD2.2 |
| 02CY771 | N/A | ? | 12 | ? |
| CP9M31 | IBM POWER9 v2 CPU (4-Core) | 4 | DD2.3 | |
| CP9M32 | IBM POWER9 v2 CPU (8-Core) | 8 | DD2.3 |
