Talk:POWER9

PowerVM Scale Out

We're not entirely sure a separate PowerVM Scale Out chip exists. PowerVM can be licensed directly for use on the OpenPOWER systems if desired. SiteAdmin (talk) 12:46, 2 January 2018 (CST)

I had definitely heard about this on the Level1Techs Forums; searching through early posts in the thread I came across a reference to an AIX Virtual User Group “webinar” wherein at ~33:00 is fairly clear about dual-socket PowerVM chips being this direct-attach RAM Scale-Out variant. I guess they could have cancelled it later on? If I feel up to it, I could go skimming through the different redbooks and see if there is some mention of dual-socket IBM i/AIX machines having a non-Cumulus chip.

This 2018 IBM POWER9 Family (PDF) document definitely seems to suggest that SMT8 Scale Out was a possible configuration, and it does have the Scale Up/Out + SMT 8/4 grid diagram; however, the “PowerVM Scale Out” machines it references seem to have more RAM slots than the AC922; suspicious. _{AbstractConcept (talk)} 15:26, 12 March 2020 (CDT)

Research for evidence of non-Nimbus LaGrange modules

I found a tweet from an ex-Rackspace employee talking about SMT8 chips also being packaged as LaGrange. I plan to add more here later. _{AbstractConcept (talk) 15:06, 12 March 2020 (CDT)}

The SMT4/SMT8 distinction is just a fusing difference, both are Nimbus AFAIK. My own analysis of IBM's POWER9 server offering concludes that most of their servers are LaGrange fused as SMT8, except for the AC922, which is Monza, the E950 and E980, which are Cumulus SMT8, and their non-FSP (and therefore non-PowerVM)- based "OpenPOWER" systems which are SMT4. (Basically a server will use CPUs fused as SMT8 if and only if it uses an FSP and not a BMC, and uses an FMC and not a BMC if and only if it uses PowerVM, AIUI.) --HLandau (talk) 02:28, 14 March 2020 (CDT)

This is my current understanding of available offerings: [1] --HLandau (talk) 02:29, 14 March 2020 (CDT)

Stepping DD 2.0 (or prior) information

Gathering place for information about DD 2.0 steppings that is unofficial or not quite ready to be included on the main page.

DD 2.0 is briefly mentioned in the v1.7 LaGrange data sheet in Table 6-19 on page 75 in section 6.4.5 AVS AC Specifications:

For DD 2.0, the pull-down internal value is 1 KΩ.

Though this is already what the table says... _{AbstractConcept (talk) 13:38, 6 July 2020 (CDT)}