Difference between revisions of "Power ISA/Privilege States"
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=== Ultravisor State === | === Ultravisor State === | ||
| − | The Ultravisor State is a | + | The Ultravisor State is a part of the IBM Protected Execution Facility (PEF) which enables support for Secure Virtual Machines (SVMs). It was first made available on POWER9 Nimbus chips with DD2.3 stepping. Like with Hypervisor State, Ultravisor State made use of a MSR bit previously marked as reserved. |
| − | It | + | It is not mentioned in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible privilege level of instructions. Prior to release of Nimbus chips with DD2.3 stepping there already was source code available which referenced the existence of an ''Ultravisor State'' [[Power ISA/Machine State Register|Machine State Register]] bit.<ref>https://patchwork.ozlabs.org/patch/719952/</ref> It will probably be part of future revisions of the Power ISA. |
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| + | ==== Timeline ==== | ||
On March 22, 2018 IBM published an article about Protected Computing using the Ultravisor state at https://developer.ibm.com/articles/l-support-protected-computing/ | On March 22, 2018 IBM published an article about Protected Computing using the Ultravisor state at https://developer.ibm.com/articles/l-support-protected-computing/ | ||
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IBM has confirmed to Raptor in direct messaging that the ultravisor state does not exist in POWER9, despite some material continuing to reference it. This information was also made public on Twitter.<ref>Lynn, Justin. [https://twitter.com/justinrwlynn/status/956772078702571520 tweet]</ref> | IBM has confirmed to Raptor in direct messaging that the ultravisor state does not exist in POWER9, despite some material continuing to reference it. This information was also made public on Twitter.<ref>Lynn, Justin. [https://twitter.com/justinrwlynn/status/956772078702571520 tweet]</ref> | ||
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=== Hypervisor State === | === Hypervisor State === | ||
Latest revision as of 20:09, 4 May 2020
Contents
States
Ultravisor State
The Ultravisor State is a part of the IBM Protected Execution Facility (PEF) which enables support for Secure Virtual Machines (SVMs). It was first made available on POWER9 Nimbus chips with DD2.3 stepping. Like with Hypervisor State, Ultravisor State made use of a MSR bit previously marked as reserved.
It is not mentioned in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible privilege level of instructions. Prior to release of Nimbus chips with DD2.3 stepping there already was source code available which referenced the existence of an Ultravisor State Machine State Register bit.[1] It will probably be part of future revisions of the Power ISA.
Timeline
On March 22, 2018 IBM published an article about Protected Computing using the Ultravisor state at https://developer.ibm.com/articles/l-support-protected-computing/
In October 2018, IBM gave a talk about Ultravisor/Protected Execution Facility at the Linux Security Summit.
A report from IBM for the Air Force Research Laboratory indicates that the Ultravisor State was already tested in a modified POWER8 processor simulation.[2]
POWER9
IBM has confirmed to Raptor in direct messaging that the ultravisor state does not exist in POWER9, despite some material continuing to reference it. This information was also made public on Twitter.[3]
Hypervisor State
Hypervisor State is indicated by the HV (bit 3) of the Machine State Register, and is normally used by a hypervisor. An operating system running without a hypervisor can run in Hypervisor State, with its userland in Problem State and avoid using Privileged State altogether.
Hypervisor State was introduced in POWER4, although for some time it was not included in documentation, appearing only as a reserved bit in the Machine State Register.[4]
Privileged State
Privileged State, also called Supervisor Mode, is normally used by an operating system running on top of a hypervisor.
Problem State
Problem State, also called User Mode, is indicated by the PR (bit 49) of the Machine State Register.
Instruction Classification
| Code | 2.07 | 3.0B | Description |
|---|---|---|---|
| P | Yes | Yes | a privileged instruction. |
| O | Yes | Yes | an instruction that is treated as privileged or nonprivileged (or hypervisor, for mtspr), depend-
ing on the SPR or PMR number. |
| PI | No | Yes | an instruction that is illegal in privileged state. |
| H | Yes | Yes | an instruction that can be executed only in hypervisor state |
| PH | Yes | No | a hypervisor privileged instruction if Category Embedded.Hypervisor is implemented; otherwise
denotes a privileged instruction. |
| M | Yes | No | an instruction that is treated as privileged or nonprivileged, depending on the value of the UCLE
bit in the MSR |
| U | No | Yes | an instruction that can be executed only in ultravisor state |
- US Patent Application 20190034666 - HARDWARE BASED ISOLATION FOR SECURE EXECUTION OF VIRTUAL MACHINES - Local Full-Text PDF w/ Illustrations: File:US020190034666A120190131-HARDWARE-BASED-ISOLATION-FOR-SECURE-EXECUTION-OF-VIRTUAL-MACHINES.pdf
- Hostboot Bootloader - Secure Memory Facility/Ultravisor Configuration References
References
- ↑ https://patchwork.ozlabs.org/patch/719952/
- ↑ File:AFRL-RI-RS-TR-2017-021.pdf. IBM. 2017-02
- ↑ Lynn, Justin. tweet
- ↑ Kerr, Jeremy. OpenPOWER: building an open-source software stack from bare metal (video). Linux.conf.au 2015
