Difference between revisions of "Turismo"
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(Created page with "{{Infobox |title = Package Information |header1 = Turismo |label2 = Processor |data2 = POWER8 |label3 = Maximum base clock |data3 = - |label4 = Maximum turbo clock...") |
JeremyRand (talk | contribs) (→Configurations: Add part numbers and core counts) |
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|label2 = Processor | |label2 = Processor | ||
|data2 = [[POWER8|POWER8]] | |data2 = [[POWER8|POWER8]] | ||
− | |label3 = | + | |label3 = Structure |
− | |data3 = | + | |data3 = [[SCM|SCM]] |
− | |label4 = Maximum | + | |label4 = Maximum base clock |
|data4 = - | |data4 = - | ||
− | |label5 = Maximum | + | |label5 = Maximum turbo clock |
|data5 = - | |data5 = - | ||
− | |label6 = | + | |label6 = Maximum [[TDP|TDP]] |
|data6 = - | |data6 = - | ||
− | |label7 = PCIe generation | + | |label7 = PCIe controllers ([[PEC|PEC]]) |
− | | | + | |data7 = - |
− | | | + | |label8 = PCIe generation |
− | | | + | |data8 = 3 |
− | | | + | |label9 = Maximum PCIe lanes |
− | | | + | |data9 = 40 |
− | | | + | |label10 = Maximum PCIe endpoints |
− | | | + | |data10 = 3 |
+ | |label11 = [[CAPI|CAPI]] interfaces | ||
+ | |data11 = 2 | ||
}} | }} | ||
+ | |||
+ | == Configurations == | ||
+ | |||
+ | {| class="wikitable sortable" | ||
+ | |+ Known Turismo parts | ||
+ | ! Part | ||
+ | ! Cores | ||
+ | |- | ||
+ | | 00UL863 | ||
+ | | 12 | ||
+ | |- | ||
+ | | 00UL010 | ||
+ | | 11 | ||
+ | |- | ||
+ | | 02AA204 | ||
+ | | 11 | ||
+ | |- | ||
+ | | 00UL864 | ||
+ | | 10 | ||
+ | |- | ||
+ | | 00UL865 | ||
+ | | 10 | ||
+ | |- | ||
+ | | 00UL866 | ||
+ | | 8 | ||
+ | |- | ||
+ | | 00UL867 | ||
+ | | 8 | ||
+ | |- | ||
+ | | 00YV366 | ||
+ | | 6 | ||
+ | |- | ||
+ | | 01HL709 | ||
+ | | 6 | ||
+ | |- | ||
+ | | 00YV860 | ||
+ | | 4 | ||
+ | |} | ||
+ | |||
+ | Sourced from [[:File:POWER8 DS v2.4 08AUG2018 pub.pdf|POWER8 data sheet v2.4]] (see Table 6-2 on page 63). | ||
+ | |||
+ | [[Category:Modules]][[Category:POWER8]] |
Latest revision as of 23:10, 19 September 2022
Turismo | |
---|---|
Processor | POWER8 |
Structure | SCM |
Maximum base clock | - |
Maximum turbo clock | - |
Maximum TDP | - |
PCIe controllers (PEC) | - |
PCIe generation | 3 |
Maximum PCIe lanes | 40 |
Maximum PCIe endpoints | 3 |
CAPI interfaces | 2 |
Configurations
Part | Cores |
---|---|
00UL863 | 12 |
00UL010 | 11 |
02AA204 | 11 |
00UL864 | 10 |
00UL865 | 10 |
00UL866 | 8 |
00UL867 | 8 |
00YV366 | 6 |
01HL709 | 6 |
00YV860 | 4 |
Sourced from POWER8 data sheet v2.4 (see Table 6-2 on page 63).