Difference between revisions of "Power ISA/Machine State Register"
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(→Bit 5 - Split Little Endian (SLE): explain oddity) |
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| − | === Bit 5 | + | === Bit 5 === |
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| + | ==== Split Little Endian (SLE) ==== | ||
{|class="wikitable" | {|class="wikitable" | ||
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|Instruction storage accesses use the value specified by MSR<sub>LE</sub>. Data storage accesses use the opposite. | |Instruction storage accesses use the value specified by MSR<sub>LE</sub>. Data storage accesses use the opposite. | ||
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| + | |||
| + | ==== Power ISA version 3 ==== | ||
| + | |||
| + | Power ISA version 3 does not define bit 5 so much as warn that, "software must ensure that this bit contains 0". It then reassure that the hardware will initialise it to 0. | ||
=== Bit 49 - Problem State (PR) === | === Bit 49 - Problem State (PR) === | ||
Revision as of 15:22, 20 January 2018
The Machine State Register, or MSR, is a Branch Facility register usually defined in Book III in the Power ISA. Among other uses, the MSR contains information about the privilege level the thread is running at. When referring to a setting in the Machine State Register, the code of the setting is in subscript directly after the abbreviation MSR. For example, documentation will refer to the Hypervisor State bit as MSRHV.
Contents
Map
| Bit | Code | Name | Defined | ||
|---|---|---|---|---|---|
| 2.07 | 3.0B | ||||
| III-S | III-E | ||||
| 0 | SF | Sixty-Four-Bit Mode | Yes | No | Yes |
| 1:2 | Reserved | No | No | No | |
| 3 | HV | Hypervisor State | Yes | No | Yes |
| 4 | Reserved | No | No | No | |
| 5 | SLE | Split Little Endian | Yes | No | Yes[note 1] |
| 6:28 | Reserved | No | No | No | |
| 29:30 | TS | Transaction State | Yes | No | Yes |
| 31 | TM | Transactional Memory Available | Yes | No | Yes |
| 32 | CM | Computation Mode | No | Yes | No |
| 33 | Reserved | No | No | No | |
| 34 | Implementation-dependant | No | Yes | No | |
| 35 | GS | Guest State | No | Yes | No |
| 36 | Implementation-dependant | No | Yes | No | |
| 37 | UCLE | User Cache Locking Enable | No | Yes | No |
| 38 | VEC | Vector Available | Yes | Yes[note 2] | Yes |
| 39 | Reserved | No | No | No | |
| 40 | VSX | VSX Available | Yes | Yes | Yes |
| 41:45 | Reserved | No | No | No | |
| 46 | CE | Critical Enable | No | Yes | No |
| 47 | Reserved | No | No | No | |
| 48 | EE | External Interrupt Enable | Yes | Yes[note 3] | Yes |
| 49 | PR | Problem State | Yes | Yes | Yes |
| 50 | FP | Floating-Point Available | Yes | Yes | Yes |
| 51 | ME | Machine Check Interrupt Enable | Yes | Yes[note 4] | Yes |
| 52 | FE0 | Floating-Point Exception Mode 0 | Yes | Yes | Yes |
| 53 | SE | Single-Step Trace Enable | Yes | Yes[note 5] | Yes[note 6] |
| 54 | BE | Branch Trace Enable | Yes | Yes[note 7] | Yes[note 6] |
| 55 | FE1 | Floating-Point Exception Mode 1 | Yes | Yes | Yes |
| 56 | Reserved | No | No | No | |
| 57 | Reserved | No | No | No | |
| 58 | IR | Instruction Relocate | Yes | Yes[note 8] | Yes |
| 59 | DR | Data Relocate | Yes | Yes[note 9] | Yes |
| 60 | Implementation-dependant | No | Yes | No | |
| 61 | PMM | Performance Monitor Mark | Yes | Yes | Yes |
| 62 | RI | Recoverable Interrupt | Yes | No | Yes |
| 63 | LE | Little-Endian Mode | Yes | No | Yes |
- ↑ Power ISA version 3.0B defines this bit as something set in hardware to be zero, and warns against changing it.
- ↑ Power ISA version 2.07 Book III-E defines this as SPV - SP/Embedded Floating-Point/Vector Available
- ↑ Power ISA version 2.07 Book III-E calls this External Enable
- ↑ Power ISA version 2.07 Book III-E calls this Machine Check Enable
- ↑ Power ISA version 2.07 Book III-E defines this as Implementation-dependent
- ↑ 6.0 6.1 Power ISA version 3.0B defines bits 53 and 54 together as TE - Trace Enable - and defines having both bits set as reserved
- ↑ Power ISA version 2.07 Book III-E defines this as DE - Debug Interrupt Enable
- ↑ Power ISA version 2.07 Book III-E defines this as IS - Instruction Address Space
- ↑ Power ISA version 2.07 Book III-E defines this as DS - Data Address Space
List
Bit 0 - Sixty-Four-Bit Mode (SF)
| 0 | The thread is in 32-bit mode |
|---|---|
| 1 | The thread is in 64-bit mode |
Bit 3 - Hypervisor State (HV)
| 0 | The thread is not in hypervisor state |
|---|---|
| 1 | The thread is in hypervisor state if MSRPR = 0 |
Bit 5
Split Little Endian (SLE)
| 0 | Instruction and data storage use the same endian-ness |
|---|---|
| 1 | Instruction storage accesses use the value specified by MSRLE. Data storage accesses use the opposite. |
Power ISA version 3
Power ISA version 3 does not define bit 5 so much as warn that, "software must ensure that this bit contains 0". It then reassure that the hardware will initialise it to 0.
Bit 49 - Problem State (PR)
| 0 | The thread is in privileged state |
|---|---|
| 1 | The thread is in problem state. |
Bit 63 - Little-Endian Mode (LE)
| 0 | The thread is in Big-Endian mode |
|---|---|
| 1 | The thread is in Little-Endian mode. |
Combined
Privilege
| MSRHV | MSRPR | State |
|---|---|---|
| 0 | 0 | privileged |
| 0 | 1 | problem |
| 1 | 0 | hypervisor |
| 1 | 1 | problem |
Endian-ness
| MSRSLE | MSRLE | Data | Instruction |
|---|---|---|---|
| 0 | 0 | Big-Endian | Big-Endian |
| 0 | 1 | Little-Endian | Little-Endian |
| 1 | 0 | Little-Endian | Big-Endian |
| 1 | 1 | Big-Endian | Little-Endian |
