Difference between revisions of "Power ISA/Machine State Register"
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m (Torpcoms moved page MSR to Machine State Register: Wiki pages here use full names) |
(add III-S info) |
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| Line 1: | Line 1: | ||
{| class="wikitable" | {| class="wikitable" | ||
|+Machine State Register | |+Machine State Register | ||
| − | !Bit | + | !rowspan="3"|Bit |
| − | !Code | + | !rowspan="3"|Code |
| − | !Name | + | !rowspan="3"|Name |
| + | !colspan="3"|Defined | ||
| + | |- | ||
| + | !colspan="2"|2.07 | ||
| + | !rowspan="2"|3.0B | ||
| + | |- | ||
| + | !III-S | ||
| + | !III-E | ||
|- | |- | ||
!0 | !0 | ||
|SF | |SF | ||
|Sixty-Four-Bit Mode | |Sixty-Four-Bit Mode | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!1:2 | !1:2 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!3 | !3 | ||
|HV | |HV | ||
|Hypervisor State | |Hypervisor State | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!4 | !4 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!5 | !5 | ||
| + | |SLE | ||
| + | |Split Little Endian | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| | | | ||
| − | | | + | |style="background:#FF9;vertical-align:middle;text-align:center;"|Yes<ref group="note">Power version ISA 3.0B defines this bit as something set in hardware to be zero, and warns against changing it.</ref> |
|- | |- | ||
!6:28 | !6:28 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!29:30 | !29:30 | ||
|TS | |TS | ||
|Transaction State | |Transaction State | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!31 | !31 | ||
|TM | |TM | ||
|Transactional Memory Available | |Transactional Memory Available | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!32:37 | !32:37 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!38 | !38 | ||
|VEC | |VEC | ||
|Vector Available | |Vector Available | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!39 | !39 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!40 | !40 | ||
|VSX | |VSX | ||
|VSX Available | |VSX Available | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!41:47 | !41:47 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!48 | !48 | ||
|EE | |EE | ||
|External Interrupt Enable | |External Interrupt Enable | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!49 | !49 | ||
|PR | |PR | ||
|Problem State | |Problem State | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!50 | !50 | ||
|FP | |FP | ||
|Floating-Point Available | |Floating-Point Available | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!51 | !51 | ||
|ME | |ME | ||
|Machine Check Interrupt Enable | |Machine Check Interrupt Enable | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!52 | !52 | ||
|FE0 | |FE0 | ||
|Floating-Point Exception Mode 0 | |Floating-Point Exception Mode 0 | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | |- | ||
| + | !53 | ||
| + | |SE | ||
| + | |Single-Step Trace Enable | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note" name="msr_te">Power ISA version 3.0B defines bits 53 and 54 together as ''TE'' - Trace Enable - and defines having both bits set as ''reserved''</ref> | ||
|- | |- | ||
| − | ! | + | !54 |
| − | | | + | |BE |
| − | |Trace Enable | + | |Branch Trace Enable |
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes<ref group="note" name="msr_te"/> | ||
|- | |- | ||
!55 | !55 | ||
|FE1 | |FE1 | ||
|Floating-Point Exception Mode 1 | |Floating-Point Exception Mode 1 | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!56:57 | !56:57 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!58 | !58 | ||
|IR | |IR | ||
|Instruction Relocate | |Instruction Relocate | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!59 | !59 | ||
|DR | |DR | ||
|Data Relocate | |Data Relocate | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!60 | !60 | ||
| | | | ||
|Reserved | |Reserved | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
| + | | | ||
| + | |style="background:#F99;vertical-align:middle;text-align:center;"|No | ||
|- | |- | ||
!61 | !61 | ||
|PMM | |PMM | ||
|Performance Monitor Mark | |Performance Monitor Mark | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!62 | !62 | ||
|RI | |RI | ||
|Recoverable Interrupt | |Recoverable Interrupt | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|- | |- | ||
!63 | !63 | ||
|LE | |LE | ||
|Little-Endian Mode | |Little-Endian Mode | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
| + | | | ||
| + | |style="background:#9F9;vertical-align:middle;text-align:center;"|Yes | ||
|} | |} | ||
| + | |||
| + | <references group="note"/> | ||
Revision as of 12:20, 20 January 2018
| Bit | Code | Name | Defined | ||
|---|---|---|---|---|---|
| 2.07 | 3.0B | ||||
| III-S | III-E | ||||
| 0 | SF | Sixty-Four-Bit Mode | Yes | Yes | |
| 1:2 | Reserved | No | No | ||
| 3 | HV | Hypervisor State | Yes | Yes | |
| 4 | Reserved | No | No | ||
| 5 | SLE | Split Little Endian | Yes | Yes[note 1] | |
| 6:28 | Reserved | No | No | ||
| 29:30 | TS | Transaction State | Yes | Yes | |
| 31 | TM | Transactional Memory Available | Yes | Yes | |
| 32:37 | Reserved | No | No | ||
| 38 | VEC | Vector Available | Yes | Yes | |
| 39 | Reserved | No | No | ||
| 40 | VSX | VSX Available | Yes | Yes | |
| 41:47 | Reserved | No | No | ||
| 48 | EE | External Interrupt Enable | Yes | Yes | |
| 49 | PR | Problem State | Yes | Yes | |
| 50 | FP | Floating-Point Available | Yes | Yes | |
| 51 | ME | Machine Check Interrupt Enable | Yes | Yes | |
| 52 | FE0 | Floating-Point Exception Mode 0 | Yes | Yes | |
| 53 | SE | Single-Step Trace Enable | Yes | Yes[note 2] | |
| 54 | BE | Branch Trace Enable | Yes | Yes[note 2] | |
| 55 | FE1 | Floating-Point Exception Mode 1 | Yes | Yes | |
| 56:57 | Reserved | No | No | ||
| 58 | IR | Instruction Relocate | Yes | Yes | |
| 59 | DR | Data Relocate | Yes | Yes | |
| 60 | Reserved | No | No | ||
| 61 | PMM | Performance Monitor Mark | Yes | Yes | |
| 62 | RI | Recoverable Interrupt | Yes | Yes | |
| 63 | LE | Little-Endian Mode | Yes | Yes | |
