Difference between revisions of "Monza"
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(Created page with "{{Infobox |title = Package Information |header1 = Monza |label2 = Processor |data2 = POWER9 |label3 = Maximum base clock |data3 = - |label4 = Maximum WOF cl...") |
JeremyRand (talk | contribs) (Add Nimbus link) |
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|label2 = Processor | |label2 = Processor | ||
|data2 = [[POWER9|POWER9]] | |data2 = [[POWER9|POWER9]] | ||
− | |label3 = | + | |label3 = Chip |
− | |data3 = | + | |data3 = [[Nimbus]] |
− | |label4 = Maximum | + | |label4 = Maximum base clock |
|data4 = - | |data4 = - | ||
− | |label5 = Maximum [[ | + | |label5 = Maximum [[WOF|WOF]] clock |
|data5 = - | |data5 = - | ||
− | |label6 = | + | |label6 = Maximum [[TDP|TDP]] |
|data6 = - | |data6 = - | ||
− | |label7 = PCIe | + | |label7 = PCIe controllers ([[PEC|PEC]]) |
− | |data7 = | + | |data7 = - |
− | |label8 = | + | |label8 = PCIe generation |
− | |data8 = | + | |data8 = 4 |
− | |label9 = Maximum PCIe | + | |label9 = Maximum PCIe lanes |
− | |data9 = | + | |data9 = 34 |
− | |label10 = | + | |label10 = Maximum PCIe endpoints |
|data10 = - | |data10 = - | ||
− | |label11 = [[ | + | |label11 = [[CAPI 2.0|CAPI 2.0]] interfaces |
|data11 = - | |data11 = - | ||
− | |label12 = [[NVLink|NVLink]] interfaces | + | |label12 = [[OpenCAPI|OpenCAPI]]/[[NVLink|NVLink]] lanes |
− | | | + | |data12 = 48 |
+ | |label13 = [[OpenCAPI|OpenCAPI]] interfaces | ||
+ | |data13 = 6 | ||
+ | |label14 = [[NVLink|NVLink]] interfaces | ||
+ | |data14 = 3 | ||
}} | }} | ||
+ | |||
+ | ''For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see [[Nimbus|Nimbus]].'' | ||
+ | |||
+ | == Configurations == | ||
+ | |||
+ | {| class="wikitable sortable" | ||
+ | |+ Known Nimbus-Monza parts | ||
+ | ! Part | ||
+ | ! Cores | ||
+ | ! [[Nimbus#Steppings|Stepping]] | ||
+ | ! Nest/Boost/Base (GHz) | ||
+ | ! Max | ||
+ | |- | ||
+ | | 03JM924 | ||
+ | | 24 | ||
+ | | DD2.3 | ||
+ | | 2.00/3.80/3.150 | ||
+ | | 300 W | ||
+ | |- | ||
+ | | 02CY598 | ||
+ | | 22 | ||
+ | | DD2.3 | ||
+ | | 2.00/3.80/3.100 | ||
+ | | 300 W | ||
+ | |- | ||
+ | | 02CY599 | ||
+ | | 20 | ||
+ | | DD2.3 | ||
+ | | 2.00/3.80/3.000 | ||
+ | | 250 W | ||
+ | |- | ||
+ | | 02CY600 | ||
+ | | 18 | ||
+ | | DD2.3 | ||
+ | | 2.00/3.80/3.450 | ||
+ | | 300 W | ||
+ | |- | ||
+ | | 02CY601 | ||
+ | | 16 | ||
+ | | DD2.3 | ||
+ | | 2.00/3.80/3.300 | ||
+ | | 250 W | ||
+ | |- | ||
+ | | 00NJ261 | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | |- | ||
+ | | 00UL016 | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | |- | ||
+ | | 00UL017 | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | |- | ||
+ | | 00UL018 | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | |- | ||
+ | | 00UL020 | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | |- | ||
+ | | 00UL021 | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | | ''unknown'' | ||
+ | |} | ||
+ | |||
+ | Sourced from [[:File:P9 ds Monza v15 18AUG2022 pub.pdf|Monza data sheet v1.5]] (see Table 6-10 on page 68) and [https://web.archive.org/web/20220905020450/https://www.ebay.com/sch/i.html?_from=R40&_trksid=p2334524.m570.l1313&_nkw=power9+monza+-lagrange&_sacat=164&LH_TitleDesc=0&_odkw=power9+monza&_osacat=164&LH_PrefLoc=2 eBay "power9 monza -lagrange"]. | ||
+ | |||
+ | == See Also == | ||
+ | |||
+ | * [[Sforza|Sforza]] POWER9 module | ||
+ | * [[LaGrange|LaGrange]] POWER9 module | ||
+ | |||
+ | == External Links == | ||
+ | |||
+ | * [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_Monza Monza Module at IBM OpenPOWER portal] | ||
+ | * [https://en.wikichip.org/wiki/ibm/cores/monza WikiChip page for Monza] | ||
+ | |||
+ | == References == | ||
+ | |||
+ | <references /> | ||
+ | |||
+ | [[Category:Modules]] | ||
+ | [[Category:POWER9]] |
Latest revision as of 07:02, 8 September 2022
Monza | |
---|---|
Processor | POWER9 |
Chip | Nimbus |
Maximum base clock | - |
Maximum WOF clock | - |
Maximum TDP | - |
PCIe controllers (PEC) | - |
PCIe generation | 4 |
Maximum PCIe lanes | 34 |
Maximum PCIe endpoints | - |
CAPI 2.0 interfaces | - |
OpenCAPI/NVLink lanes | 48 |
OpenCAPI interfaces | 6 |
NVLink interfaces | 3 |
For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see Nimbus.
Configurations
Part | Cores | Stepping | Nest/Boost/Base (GHz) | Max |
---|---|---|---|---|
03JM924 | 24 | DD2.3 | 2.00/3.80/3.150 | 300 W |
02CY598 | 22 | DD2.3 | 2.00/3.80/3.100 | 300 W |
02CY599 | 20 | DD2.3 | 2.00/3.80/3.000 | 250 W |
02CY600 | 18 | DD2.3 | 2.00/3.80/3.450 | 300 W |
02CY601 | 16 | DD2.3 | 2.00/3.80/3.300 | 250 W |
00NJ261 | unknown | unknown | unknown | unknown |
00UL016 | unknown | unknown | unknown | unknown |
00UL017 | unknown | unknown | unknown | unknown |
00UL018 | unknown | unknown | unknown | unknown |
00UL020 | unknown | unknown | unknown | unknown |
00UL021 | unknown | unknown | unknown | unknown |
Sourced from Monza data sheet v1.5 (see Table 6-10 on page 68) and eBay "power9 monza -lagrange".