Difference between revisions of "LaGrange"

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|label2 = Processor
 
|label2 = Processor
 
|data2 = [[POWER9|POWER9]]
 
|data2 = [[POWER9|POWER9]]
−
|label3 = Maximum base clock
+
|label3 = Chip
−
|data3 = -
+
|data3 = [[Nimbus]]
−
|label4 = Maximum [[WOF|WOF]] clock
+
|label4 = Maximum base clock
 
|data4 = -
 
|data4 = -
−
|label5 = Maximum [[TDP|TDP]]
+
|label5 = Maximum [[WOF|WOF]] clock
 
|data5 = -
 
|data5 = -
−
|label6 = PCIe controllers ([[PEC|PEC]])
+
|label6 = Maximum [[TDP|TDP]]
 
|data6 = -
 
|data6 = -
−
|label7 = PCIe generation
+
|label7 = PCIe controllers ([[PEC|PEC]])
−
|data7 = 4
+
|data7 = -
−
|label8 = Maximum PCIe lanes
+
|label8 = PCIe generation
−
|data8 = 42
+
|data8 = 4
−
|label9 = Maximum PCIe endpoints
+
|label9 = Maximum PCIe lanes
−
|data9 = -
+
|data9 = 42
−
|label10 = [[CAPI 2.0|CAPI 2.0]] interfaces
+
|label10 = Maximum PCIe endpoints
 
|data10 = -
 
|data10 = -
−
|label11 = [[OpenCAPI|OpenCAPI]] interfaces
+
|label11 = [[CAPI 2.0|CAPI 2.0]] interfaces
 
|data11 = -
 
|data11 = -
−
|label12 = [[NVLink|NVLink]] interfaces
+
|label12 = [[OpenCAPI|OpenCAPI]]/[[NVLink|NVLink]] lanes
−
|data12 = -
+
|data12 = 16
 +
|label13 = [[OpenCAPI|OpenCAPI]] interfaces
 +
|data13 = 2
 +
|label14 = [[NVLink|NVLink]] interfaces
 +
|data14 = 1
 
}}
 
}}
  
−
[[Category:Nimbus Modules]]
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''For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see [[Nimbus|Nimbus]].''
 +
 
 +
'''LaGrange''' is the codename for a [[POWER9]], [[Nimbus]] chip, CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the [[Sforza]] module, and the maximum OpenCAPI/NVLink connectivity of the [[Monza]] module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules.
 +
 
 +
LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board.
 +
 
 +
LaGrange will be used for the upcoming RCS [[Condor|Condor]] board, albeit in a single-socket configuration.
 +
 
 +
{| class="wikitable sortable"
 +
|+ Known Nimbus-LaGrange parts
 +
! Part
 +
! Cores
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! [[Nimbus#Steppings|Stepping]]
 +
! Nest/Boost/Base (GHz)
 +
! Max
 +
|-
 +
| 02CY069
 +
|rowspan=2| 22
 +
| DD2.2
 +
|rowspan=2| 2.00/3.80/2.90
 +
|rowspan=2| 225 W
 +
|-
 +
| 02CY574
 +
| DD2.3
 +
|-
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| 02CY254
 +
|rowspan=2| 20
 +
| DD2.2
 +
|rowspan=2| 2.00/3.80/2.90
 +
|rowspan=2| 225 W
 +
|-
 +
| 02CY582
 +
| DD2.3
 +
|-
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| 02CY249
 +
|rowspan=3| 16
 +
| DD2.2
 +
| 2.00/3.90/3.40
 +
|rowspan=3| 225 W
 +
|-
 +
| 02CY584
 +
| DD2.3
 +
| 2.00/4.00/3.35
 +
|-
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| 02AA947
 +
| DD2.1
 +
| 2.00/3.80/2.95
 +
|-
 +
| 02CY057
 +
|rowspan=2| 18
 +
| DD2.2
 +
|rowspan=2| 2.00/3.80/2.80
 +
|rowspan=2| 190 W
 +
|-
 +
| 02CY575
 +
| DD2.3
 +
|-
 +
| 02WP188
 +
| 12
 +
| DD2.3
 +
| 2.00/3.80/2.80
 +
| 160 W
 +
|}
 +
 
 +
Sourced from [[:File:POWER9 LaGrange ds v17 28MAR2019 pub.pdf|LaGrange data sheet v1.7]] (see Table 6-10 on page 66) and [[:File:POWER9 LaGrange ds v18 14AUG2019 pub.pdf|LaGrange data sheet v1.8]] (see Table 6-10 on page 66).
 +
 
 +
== See Also ==
 +
 
 +
* [[Sforza|Sforza]] POWER9 module
 +
* [[Monza|Monza]] POWER9 module
 +
 
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== External Links ==
 +
 
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* [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_LaGrange LaGrange Module at IBM OpenPOWER portal]
 +
* [https://en.wikichip.org/wiki/ibm/cores/lagrange WikiChip page for LaGrange]
 +
 
 +
[[Category:Modules]]
 +
[[Category:POWER9]]

Latest revision as of 08:54, 6 September 2022

Package Information
LaGrange
Processor POWER9
Chip Nimbus
Maximum base clock -
Maximum WOF clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 4
Maximum PCIe lanes 42
Maximum PCIe endpoints -
CAPI 2.0 interfaces -
OpenCAPI/NVLink lanes 16
OpenCAPI interfaces 2
NVLink interfaces 1

For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see Nimbus.

LaGrange is the codename for a POWER9, Nimbus chip, CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the Sforza module, and the maximum OpenCAPI/NVLink connectivity of the Monza module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules.

LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board.

LaGrange will be used for the upcoming RCS Condor board, albeit in a single-socket configuration.

Known Nimbus-LaGrange parts
Part Cores Stepping Nest/Boost/Base (GHz) Max
02CY069 22 DD2.2 2.00/3.80/2.90 225 W
02CY574 DD2.3
02CY254 20 DD2.2 2.00/3.80/2.90 225 W
02CY582 DD2.3
02CY249 16 DD2.2 2.00/3.90/3.40 225 W
02CY584 DD2.3 2.00/4.00/3.35
02AA947 DD2.1 2.00/3.80/2.95
02CY057 18 DD2.2 2.00/3.80/2.80 190 W
02CY575 DD2.3
02WP188 12 DD2.3 2.00/3.80/2.80 160 W

Sourced from LaGrange data sheet v1.7 (see Table 6-10 on page 66) and LaGrange data sheet v1.8 (see Table 6-10 on page 66).

See Also

External Links

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