Difference between revisions of "LaGrange"

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(Created page with "{{Infobox |title = Package Information |header1 = LaGrange |label2 = Processor |data2 = POWER9 |label3 = Maximum base clock |data3 = - |label4 = Maximum WOF...")
 
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|label2 = Processor
 
|label2 = Processor
 
|data2 = [[POWER9|POWER9]]
 
|data2 = [[POWER9|POWER9]]
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|label3 = Maximum base clock
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|label3 = Chip
−
|data3 = -
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|data3 = [[Nimbus]]
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|label4 = Maximum [[WOF|WOF]] clock
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|label4 = Maximum base clock
 
|data4 = -
 
|data4 = -
−
|label5 = Maximum [[TDP|TDP]]
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|label5 = Maximum [[WOF|WOF]] clock
 
|data5 = -
 
|data5 = -
−
|label6 = PCIe controllers ([[PEC|PEC]])
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|label6 = Maximum [[TDP|TDP]]
 
|data6 = -
 
|data6 = -
−
|label7 = PCIe generation
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|label7 = PCIe controllers ([[PEC|PEC]])
−
|data7 = 4
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|data7 = -
−
|label8 = Maximum PCIe lanes
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|label8 = PCIe generation
−
|data8 = 42
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|data8 = 4
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|label9 = Maximum PCIe endpoints
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|label9 = Maximum PCIe lanes
−
|data9 = -
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|data9 = 42
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|label10 = [[CAPI 2.0|CAPI 2.0]] interfaces
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|label10 = Maximum PCIe endpoints
 
|data10 = -
 
|data10 = -
−
|label11 = [[OpenCAPI|OpenCAPI]] interfaces
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|label11 = [[CAPI 2.0|CAPI 2.0]] interfaces
 
|data11 = -
 
|data11 = -
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|label12 = [[NVLink|NVLink]] interfaces
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|label12 = [[OpenCAPI|OpenCAPI]]/[[NVLink|NVLink]] lanes
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|data12 = -
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|data12 = 16
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|label13 = [[OpenCAPI|OpenCAPI]] interfaces
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|data13 = 2
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|label14 = [[NVLink|NVLink]] interfaces
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|data14 = 1
 
}}
 
}}
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''For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see [[Nimbus|Nimbus]].''
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'''LaGrange''' is the codename for a [[POWER9]], [[Nimbus]] chip, CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the [[Sforza]] module, and the maximum OpenCAPI/NVLink connectivity of the [[Monza]] module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules.
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LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board.
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LaGrange will be used for the upcoming RCS [[Condor|Condor]] board, albeit in a single-socket configuration.
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{| class="wikitable sortable"
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|+ Known Nimbus-LaGrange parts
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! Part
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! Cores
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! [[Nimbus#Steppings|Stepping]]
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! Nest/Boost/Base (GHz)
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! Max
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|-
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| 02CY069
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|rowspan=2| 22
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| DD2.2
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|rowspan=2| 2.00/3.80/2.90
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|rowspan=2| 225 W
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|-
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| 02CY574
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| DD2.3
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|-
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| 02CY254
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|rowspan=2| 20
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| DD2.2
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|rowspan=2| 2.00/3.80/2.90
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|rowspan=2| 225 W
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|-
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| 02CY582
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| DD2.3
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|-
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| 02CY249
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|rowspan=3| 16
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| DD2.2
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| 2.00/3.90/3.40
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|rowspan=3| 225 W
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|-
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| 02CY584
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| DD2.3
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| 2.00/4.00/3.35
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|-
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| 02AA947
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| DD2.1
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| 2.00/3.80/2.95
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|-
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| 02CY057
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|rowspan=2| 18
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| DD2.2
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|rowspan=2| 2.00/3.80/2.80
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|rowspan=2| 190 W
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|-
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| 02CY575
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| DD2.3
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|-
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| 02WP188
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| 12
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| DD2.3
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| 2.00/3.80/2.80
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| 160 W
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|}
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Sourced from [[:File:POWER9 LaGrange ds v17 28MAR2019 pub.pdf|LaGrange data sheet v1.7]] (see Table 6-10 on page 66) and [[:File:POWER9 LaGrange ds v18 14AUG2019 pub.pdf|LaGrange data sheet v1.8]] (see Table 6-10 on page 66).
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== See Also ==
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* [[Sforza|Sforza]] POWER9 module
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* [[Monza|Monza]] POWER9 module
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== External Links ==
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* [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_LaGrange LaGrange Module at IBM OpenPOWER portal]
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* [https://en.wikichip.org/wiki/ibm/cores/lagrange WikiChip page for LaGrange]
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[[Category:Modules]]
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[[Category:POWER9]]

Latest revision as of 08:54, 6 September 2022

Package Information
LaGrange
Processor POWER9
Chip Nimbus
Maximum base clock -
Maximum WOF clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 4
Maximum PCIe lanes 42
Maximum PCIe endpoints -
CAPI 2.0 interfaces -
OpenCAPI/NVLink lanes 16
OpenCAPI interfaces 2
NVLink interfaces 1

For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see Nimbus.

LaGrange is the codename for a POWER9, Nimbus chip, CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the Sforza module, and the maximum OpenCAPI/NVLink connectivity of the Monza module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules.

LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board.

LaGrange will be used for the upcoming RCS Condor board, albeit in a single-socket configuration.

Known Nimbus-LaGrange parts
Part Cores Stepping Nest/Boost/Base (GHz) Max
02CY069 22 DD2.2 2.00/3.80/2.90 225 W
02CY574 DD2.3
02CY254 20 DD2.2 2.00/3.80/2.90 225 W
02CY582 DD2.3
02CY249 16 DD2.2 2.00/3.90/3.40 225 W
02CY584 DD2.3 2.00/4.00/3.35
02AA947 DD2.1 2.00/3.80/2.95
02CY057 18 DD2.2 2.00/3.80/2.80 190 W
02CY575 DD2.3
02WP188 12 DD2.3 2.00/3.80/2.80 160 W

Sourced from LaGrange data sheet v1.7 (see Table 6-10 on page 66) and LaGrange data sheet v1.8 (see Table 6-10 on page 66).

See Also

External Links

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