Difference between revisions of "LaGrange"

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(add category)
(add nimbus chip)
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|label2 = Processor
 
|label2 = Processor
 
|data2 = [[POWER9|POWER9]]
 
|data2 = [[POWER9|POWER9]]
−
|label3 = Maximum base clock
+
|label3 = Chip
−
|data3 = -
+
|data3 = Nimbus
−
|label4 = Maximum [[WOF|WOF]] clock
+
|label4 = Maximum base clock
 
|data4 = -
 
|data4 = -
−
|label5 = Maximum [[TDP|TDP]]
+
|label5 = Maximum [[WOF|WOF]] clock
 
|data5 = -
 
|data5 = -
−
|label6 = PCIe controllers ([[PEC|PEC]])
+
|label6 = Maximum [[TDP|TDP]]
 
|data6 = -
 
|data6 = -
−
|label7 = PCIe generation
+
|label7 = PCIe controllers ([[PEC|PEC]])
−
|data7 = 4
+
|data7 = -
−
|label8 = Maximum PCIe lanes
+
|label8 = PCIe generation
−
|data8 = 42
+
|data8 = 4
−
|label9 = Maximum PCIe endpoints
+
|label9 = Maximum PCIe lanes
−
|data9 = -
+
|data9 = 42
−
|label10 = [[CAPI 2.0|CAPI 2.0]] interfaces
+
|label10 = Maximum PCIe endpoints
 
|data10 = -
 
|data10 = -
−
|label11 = [[OpenCAPI|OpenCAPI]] interfaces
+
|label11 = [[CAPI 2.0|CAPI 2.0]] interfaces
 
|data11 = -
 
|data11 = -
−
|label12 = [[NVLink|NVLink]] interfaces
+
|label12 = [[OpenCAPI|OpenCAPI]] interfaces
 
|data12 = -
 
|data12 = -
 +
|label13 = [[NVLink|NVLink]] interfaces
 +
|data13 = -
 
}}
 
}}
  
 
[[Category:Nimbus Modules]]
 
[[Category:Nimbus Modules]]

Revision as of 09:57, 29 December 2017

Package Information
LaGrange
Processor POWER9
Chip Nimbus
Maximum base clock -
Maximum WOF clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 4
Maximum PCIe lanes 42
Maximum PCIe endpoints -
CAPI 2.0 interfaces -
OpenCAPI interfaces -
NVLink interfaces -
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