Difference between revisions of "LaGrange"
Jump to navigation
Jump to search
(Adding part from datasheet v1.7) |
|||
Line 29: | Line 29: | ||
|data14 = 1 | |data14 = 1 | ||
}} | }} | ||
+ | |||
+ | {| class="wikitable sortable" | ||
+ | |+ Known Nimbus-LaGrange parts | ||
+ | ! Part | ||
+ | ! Cores | ||
+ | ! Stepping | ||
+ | ! Nest/Boost/Base (GHz) | ||
+ | ! Max | ||
+ | |- | ||
+ | | 02CY069 | ||
+ | | 22 | ||
+ | | | ||
+ | | 2.00/3.80/2.90 | ||
+ | | 225 W | ||
+ | |- | ||
+ | | 02CY254 | ||
+ | | 20 | ||
+ | | | ||
+ | | 2.00/3.80/2.90 | ||
+ | | 225 W | ||
+ | |- | ||
+ | | 02CY249 | ||
+ | | 16 | ||
+ | | | ||
+ | | 2.00/3.80/3.40 | ||
+ | | 225 W | ||
+ | |- | ||
+ | | 02CY057 | ||
+ | | 18 | ||
+ | | | ||
+ | | 2.00/3.80/2.80 | ||
+ | | 190 W | ||
+ | |} | ||
== External Links == | == External Links == |
Revision as of 23:00, 2 May 2020
LaGrange | |
---|---|
Processor | POWER9 |
Chip | Nimbus |
Maximum base clock | - |
Maximum WOF clock | - |
Maximum TDP | - |
PCIe controllers (PEC) | - |
PCIe generation | 4 |
Maximum PCIe lanes | 42 |
Maximum PCIe endpoints | - |
CAPI 2.0 interfaces | - |
OpenCAPI/NVLink lanes | 16 |
OpenCAPI interfaces | 2 |
NVLink interfaces | 1 |
Part | Cores | Stepping | Nest/Boost/Base (GHz) | Max |
---|---|---|---|---|
02CY069 | 22 | 2.00/3.80/2.90 | 225 W | |
02CY254 | 20 | 2.00/3.80/2.90 | 225 W | |
02CY249 | 16 | 2.00/3.80/3.40 | 225 W | |
02CY057 | 18 | 2.00/3.80/2.80 | 190 W |