Difference between revisions of "OpenPOWER Firmware"

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(Major revision, add more firmware pieces)
Line 14: Line 14:
 
| SBE core (on CPU chip)
 
| SBE core (on CPU chip)
 
| eFuses
 
| eFuses
 +
[https://git.raptorcs.com/git/talos-sbe/tree/src/boot/otprom_init.S Source]
 
|
 
|
 
* very first instructions executed
 
* very first instructions executed
 
* loads SBE firmware from SEEPROM into SBE core
 
* loads SBE firmware from SEEPROM into SBE core
 
|-
 
|-
−
| [[Self-Boot Engine|Self-Boot Engine]] (SBE)
+
| [[Self-Boot Engine|Self-Boot Engine]] (SBE) firmware
 
| SBE core (on CPU chip)
 
| SBE core (on CPU chip)
 
| SBE SEEPROM
 
| SBE SEEPROM
 +
[https://git.raptorcs.com/git/talos-sbe/tree/ Source]
 
|
 
|
 
* initialises CPU core
 
* initialises CPU core
Line 29: Line 31:
 
| CPU core
 
| CPU core
 
| SBE SEEPROM
 
| SBE SEEPROM
 +
[https://git.raptorcs.com/git/talos-hostboot/tree/src/bootloader Source]
 
|
 
|
 
* first code which runs on main CPU cores; loads and executes rest of Hostboot
 
* first code which runs on main CPU cores; loads and executes rest of Hostboot
Line 36: Line 39:
 
| CPU core
 
| CPU core
 
| PNOR SPI Flash
 
| PNOR SPI Flash
 +
[https://git.raptorcs.com/git/talos-hostboot/tree/ Source]
 
|
 
|
 
* initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
 
* initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
Line 43: Line 47:
 
| CPU core
 
| CPU core
 
| PNOR SPI Flash
 
| PNOR SPI Flash
 +
[https://git.raptorcs.com/git/talos-skiboot/tree/ Source]
 
|
 
|
 
* initialises PCIe controllers, device trees, real time clock, NVlink, sensors
 
* initialises PCIe controllers, device trees, real time clock, NVlink, sensors
Line 52: Line 57:
 
| CPU core
 
| CPU core
 
| PNOR SPI Flash
 
| PNOR SPI Flash
 +
[https://git.raptorcs.com/git/talos-petitboot/ Source]
 
|
 
|
 
* [[Skiroot]] refers to the Linux kernel and initramfs which runs from RAM
 
* [[Skiroot]] refers to the Linux kernel and initramfs which runs from RAM
Line 57: Line 63:
 
* [[Petitboot]] loads operating system via kexec
 
* [[Petitboot]] loads operating system via kexec
 
|-
 
|-
−
| [[On-Chip Controller|On-Chip Controller]] (OCC)
+
| [[On-Chip Controller|On-Chip Controller]] (OCC) firmware
 
| OCC core (on CPU chip)
 
| OCC core (on CPU chip)
 
| PNOR SPI Flash
 
| PNOR SPI Flash
 +
[https://git.raptorcs.com/git/talos-occ/tree/ Source]
 
|
 
|
 
* thermal regulation of CPU chip, turbo frequency selection, voltage ID selection, power measurement, etc.
 
* thermal regulation of CPU chip, turbo frequency selection, voltage ID selection, power measurement, etc.
 +
|-
 +
| [[CME]] [[HCODE]]
 +
| [[CME]] cores (on CPU chip)
 +
| PNOR SPI Flash
 +
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 +
|
 +
* The [[Core Management Engine|Core Management Engines]] are auxillary cores used for power management purposes. They are ultimately responsible to the OCC. There is one CME for every two SMT4 cores.
 +
|-
 +
| [[SGPE]] and [[PGPE]] [[HCODE]]
 +
| [[GPE|General Purpose Engine]] cores (on CPU chip)
 +
| PNOR SPI Flash
 +
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 +
|
 +
* Auxillary cores which assist, and are managed by, the OCC.
 +
* The [[SGPE|Stop GPEs]] (SGPEs) are part of the mechanism for resuming execution after a STOP instruction is executed (which is a Power ISA instruction which halts the processor).
 +
* The [[PGPE|Pstate GPEs]] (PGPEs) perform pstate management.
 +
|-
 +
| [[IOPPE]] [[HCODE]]
 +
| [[IOPPE]] cores (on CPU chip)
 +
| PNOR SPI Flash
 +
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 +
|
 +
* Involved in CAPI support.
 +
|- style="background-color:#e0e0e0;"
 +
| [[OpenBMC]]
 +
| BMC chip
 +
| BMC SPI Flash
 +
[https://git.raptorcs.com/git/talos-openbmc/tree/ Source]
 +
|
 +
<small>(This is not part of OpenPOWER firmware, but is mentioned to give a picture of the division of responsibilities. Not all POWER9 systems use a BMC; IBM systems use a [[FSP]].)</small>
 +
* Turns system power rails on and off to energise and deenergise CPU modules, RAM, etc.
 +
* Sends commands to CPU modules over [[FSI]] to commence booting.
 +
* Provides access to PNOR SPI flash containing host firmware via LPC.
 +
* Receives core temperature information from the [[OCC]]; decides and sets fan speeds.
 +
* Powers off system if [[OCC]] indicates catastrophic temperature.
 
|}
 
|}
 +
 +
[[File:P9_ppe_instances.png|thumb|Diagram of main and auxillary cores on [[POWER9]]]]
  
 
== Process ==
 
== Process ==
Line 86: Line 130:
 
== External Links ==
 
== External Links ==
  
−
* [https://github.com/open-power/docs OpenPOWER github account]
+
* [https://github.com/open-power/docs OpenPOWER firmware source code on GitHub]
−
* [https://github.com/open-power/docs OpenPOWER firmware documentation]
+
* For a better understanding of OpenPOWER firmware and boot processes, see:
−
* [https://blog.jms.id.au/2015/07/openpower-firmware-stack/ OpenPower Firmware Stack] - Joel's Weblog
+
** [https://github.com/open-power/docs/blob/master/hostboot/HostBoot_PG.md Overview of Boot Process]
 +
** [https://github.com/open-power/docs/blob/master/hostboot/P9_Boot_Flow_OpenPOWER.pdf P9 Boot Flow]
 +
** [https://github.com/open-power/docs More OpenPOWER firmware documentation]
 +
** [https://blog.jms.id.au/2015/07/openpower-firmware-stack/ OpenPOWER Firmware Stack] - Joel's Weblog
  
 
[[Category:Firmware]]
 
[[Category:Firmware]]

Revision as of 12:26, 2 August 2018

OpenPOWER Firmware is an open-source alternative to OpenFirmware and proprietary IBM firmware used on Power machines.[1] It is a general name for many separate pieces of software used to start recent Power Architecture chips made by IBM.[2]

OpenBMC is a separate project that creates firmware for the Baseboard Management Controller.

Components

Firmware Executed on Loaded from Function
OTPROM SBE core (on CPU chip) eFuses

Source

  • very first instructions executed
  • loads SBE firmware from SEEPROM into SBE core
Self-Boot Engine (SBE) firmware SBE core (on CPU chip) SBE SEEPROM

Source

  • initialises CPU core
  • loads Hostboot Bootloader
  • backup copy stored on PNOR SPI Flash, used to stage SBE firmware updates
Hostboot Bootloader (HBBL) CPU core SBE SEEPROM

Source

  • first code which runs on main CPU cores; loads and executes rest of Hostboot
  • responsible for verifying integrity of Hostboot when secure boot is enabled, so this part of Hostboot is stored on the SBE SEEPROM, even though its source code lives inside the Hostboot repository
Hostboot CPU core PNOR SPI Flash

Source

  • initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
  • finally, chainloads Skiboot
Skiboot CPU core PNOR SPI Flash

Source

  • initialises PCIe controllers, device trees, real time clock, NVlink, sensors
  • loads OCC firmware and starts OCC running
  • implements OpenPOWER Abstraction Layer (OPAL) for OS runtime services; remains resident in RAM after OS boot
  • finally, chainloads Skiroot
Skiroot/Petitboot CPU core PNOR SPI Flash

Source

  • Skiroot refers to the Linux kernel and initramfs which runs from RAM
  • Contains Petitboot, a userspace application which provides a boot menu
  • Petitboot loads operating system via kexec
On-Chip Controller (OCC) firmware OCC core (on CPU chip) PNOR SPI Flash

Source

  • thermal regulation of CPU chip, turbo frequency selection, voltage ID selection, power measurement, etc.
CME HCODE CME cores (on CPU chip) PNOR SPI Flash

Source

  • The Core Management Engines are auxillary cores used for power management purposes. They are ultimately responsible to the OCC. There is one CME for every two SMT4 cores.
SGPE and PGPE HCODE General Purpose Engine cores (on CPU chip) PNOR SPI Flash

Source

  • Auxillary cores which assist, and are managed by, the OCC.
  • The Stop GPEs (SGPEs) are part of the mechanism for resuming execution after a STOP instruction is executed (which is a Power ISA instruction which halts the processor).
  • The Pstate GPEs (PGPEs) perform pstate management.
IOPPE HCODE IOPPE cores (on CPU chip) PNOR SPI Flash

Source

  • Involved in CAPI support.
OpenBMC BMC chip BMC SPI Flash

Source

(This is not part of OpenPOWER firmware, but is mentioned to give a picture of the division of responsibilities. Not all POWER9 systems use a BMC; IBM systems use a FSP.)

  • Turns system power rails on and off to energise and deenergise CPU modules, RAM, etc.
  • Sends commands to CPU modules over FSI to commence booting.
  • Provides access to PNOR SPI flash containing host firmware via LPC.
  • Receives core temperature information from the OCC; decides and sets fan speeds.
  • Powers off system if OCC indicates catastrophic temperature.
Diagram of main and auxillary cores on POWER9

Process

  1. SBE executes OTPROM, which loads SEEPROM firmware into SBE PIBMEM
  2. SBE executes SEEPROM firmware
  3. OpenBMC uses FSI interface to start SBE
  4. SBE loads Hostboot
  5. Hostboot loads Skiboot
  6. Skiboot loads OCC, Skiroot
  7. Petitboot application within Skiroot loads the operating system
  8. OS talks to firmware through OPAL

References

  1. ↑ Kerr, Jeremy. OpenPOWER: building an open-source software stack from bare metal. LCA 2015 - video on YouTube
  2. ↑ Smith, Stewart. Adventures in OpenPOWER Firmware. LCA 2016 - video on YouTube

See also

External Links

Retrieved from "https://wiki.raptorcs.com/w/index.php?title=OpenPOWER_Firmware&oldid=1171"