Difference between revisions of "OpenPOWER Firmware"

From RCS Wiki
Jump to navigation Jump to search
(clarify that on TalosII boards the FSI debugging interface is used to override the normal POWER9 boot sequence)
(Cleanup)
Line 20: Line 20:
 
| [[Self-Boot Engine|Self-Boot Engine]] (SBE)
 
| [[Self-Boot Engine|Self-Boot Engine]] (SBE)
 
| SBE core (on CPU chip)
 
| SBE core (on CPU chip)
−
| SEEPROM
+
| SBE SEEPROM
 
|
 
|
 
* initialises CPU core
 
* initialises CPU core
−
* loads Hostboot
+
* loads Hostboot Bootloader
 +
* backup copy stored on PNOR SPI Flash, used to stage SBE firmware updates
 +
|-
 +
| Hostboot Bootloader (HBBL)
 +
| CPU core
 +
| SBE SEEPROM
 +
|
 +
* first code which runs on main CPU cores; loads and executes rest of Hostboot
 +
* responsible for verifying integrity of Hostboot when secure boot is enabled, so this part of Hostboot is stored on the SBE SEEPROM, even though its source code lives inside the Hostboot repository
 
|-
 
|-
 
| [[Hostboot|Hostboot]]
 
| [[Hostboot|Hostboot]]
 
| CPU core
 
| CPU core
−
| SPI Flash
+
| PNOR SPI Flash
 
|
 
|
−
* loads Skiboot
+
* initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
−
* inits DRAM (zeroing for ECC mem.), Processor Bus, Memory buffer
+
* finally, chainloads Skiboot
 
|-
 
|-
 
| [[Skiboot|Skiboot]]
 
| [[Skiboot|Skiboot]]
 
| CPU core
 
| CPU core
 +
| PNOR SPI Flash
 
|
 
|
−
|
+
* initialises PCIe controllers, device trees, real time clock, NVlink, sensors
−
* implements [[OpenPOWER Abstraction Layer|OpenPOWER Abstraction Layer]] (OPAL) for OS runtime services
+
* loads OCC firmware and starts OCC running
−
* setup PCIe, device tree, real time clock, NVlink, sensors
+
* implements [[OpenPOWER Abstraction Layer|OpenPOWER Abstraction Layer]] (OPAL) for OS runtime services; remains resident in RAM after OS boot
−
* loads Petitboot, OCC
+
* finally, chainloads Skiroot
 
|-
 
|-
−
| [[Petitboot|Petitboot]]
+
| [[Skiroot]]/[[Petitboot|Petitboot]]
 
| CPU core
 
| CPU core
 +
| PNOR SPI Flash
 
|
 
|
−
|
+
* [[Skiroot]] refers to the Linux kernel and initramfs which runs from RAM
−
* boot menu
+
* Contains [[Petitboot]], a userspace application which provides a boot menu
−
* loads operating system
+
* [[Petitboot]] loads operating system via kexec
 
|-
 
|-
 
| [[On-Chip Controller|On-Chip Controller]] (OCC)
 
| [[On-Chip Controller|On-Chip Controller]] (OCC)
 
| OCC core (on CPU chip)
 
| OCC core (on CPU chip)
−
|
+
| PNOR SPI Flash
 
|
 
|
 
* thermal regulation on CPU chip
 
* thermal regulation on CPU chip
Line 61: Line 71:
 
# [[Self-Boot Engine|SBE]] loads Hostboot   
 
# [[Self-Boot Engine|SBE]] loads Hostboot   
 
# [[Hostboot|Hostboot]] loads Skiboot
 
# [[Hostboot|Hostboot]] loads Skiboot
−
# [[Skiboot|Skiboot]] loads OCC, Petitboot
+
# [[Skiboot|Skiboot]] loads [[OCC]], [[Skiroot]]
−
# [[Petitboot|Petitboot]] loads the operating system
+
# [[Petitboot|Petitboot]] application within [[Skiroot]] loads the operating system
−
# operating system talks to firmware through [[OpenPOWER Abstraction Layer|OPAL]]
+
# OS talks to firmware through [[OpenPOWER Abstraction Layer|OPAL]]
  
 
== References ==
 
== References ==

Revision as of 19:36, 30 July 2018

OpenPOWER Firmware is an open-source alternative to OpenFirmware and proprietary IBM firmware used on Power machines.[1] It is a general name for many separate pieces of software used to start recent Power Architecture chips made by IBM.[2]

OpenBMC is a separate project that creates firmware for the Baseboard Management Controller.

Components

Firmware Executed on Loaded from Function
OTPROM SBE core (on CPU chip) eFuses
  • very first instructions executed
  • loads SBE firmware from SEEPROM into SBE core
Self-Boot Engine (SBE) SBE core (on CPU chip) SBE SEEPROM
  • initialises CPU core
  • loads Hostboot Bootloader
  • backup copy stored on PNOR SPI Flash, used to stage SBE firmware updates
Hostboot Bootloader (HBBL) CPU core SBE SEEPROM
  • first code which runs on main CPU cores; loads and executes rest of Hostboot
  • responsible for verifying integrity of Hostboot when secure boot is enabled, so this part of Hostboot is stored on the SBE SEEPROM, even though its source code lives inside the Hostboot repository
Hostboot CPU core PNOR SPI Flash
  • initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
  • finally, chainloads Skiboot
Skiboot CPU core PNOR SPI Flash
  • initialises PCIe controllers, device trees, real time clock, NVlink, sensors
  • loads OCC firmware and starts OCC running
  • implements OpenPOWER Abstraction Layer (OPAL) for OS runtime services; remains resident in RAM after OS boot
  • finally, chainloads Skiroot
Skiroot/Petitboot CPU core PNOR SPI Flash
  • Skiroot refers to the Linux kernel and initramfs which runs from RAM
  • Contains Petitboot, a userspace application which provides a boot menu
  • Petitboot loads operating system via kexec
On-Chip Controller (OCC) OCC core (on CPU chip) PNOR SPI Flash
  • thermal regulation on CPU chip

Process

  1. SBE executes OTPROM, which loads SEEPROM firmware into SBE PIBMEM
  2. SBE executes SEEPROM firmware
  3. OpenBMC uses FSI interface to start SBE
  4. SBE loads Hostboot
  5. Hostboot loads Skiboot
  6. Skiboot loads OCC, Skiroot
  7. Petitboot application within Skiroot loads the operating system
  8. OS talks to firmware through OPAL

References

  1. ↑ Kerr, Jeremy. OpenPOWER: building an open-source software stack from bare metal. LCA 2015 - video on YouTube
  2. ↑ Smith, Stewart. Adventures in OpenPOWER Firmware. LCA 2016 - video on YouTube

See also

External Links

Retrieved from "https://wiki.raptorcs.com/w/index.php?title=OpenPOWER_Firmware&oldid=1165"