Difference between revisions of "User:JSharp"

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(+OpenPOWER Developer Congress 2017 for mining/review for docs in presos)
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* Mine/Review [https://openpowerfoundation.org/openpower-summit-2016/] for additional documentation
 
* Mine/Review [https://openpowerfoundation.org/openpower-summit-2016/] for additional documentation
 
* Also Mine/Review [http://developercongress2017.openpowerfoundation.org/presentations/]
 
* Also Mine/Review [http://developercongress2017.openpowerfoundation.org/presentations/]
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** Especially [http://developercongress2017.openpowerfoundation.org/wp-content/uploads/2017/05/Part3-On-Chip-Controller-OCC-Tutorial-1.pdf OCC Tutorial](!) Heaps of good stuff there.
  
== T2/x86 FSC Heterogeneous Cluster (veritates@kraftwerk) ==
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=== Projects (in order of interest/work likelihood) ===
  
Includes Primary User Interface/System Element (in the IBM sense) components. A work in progress, incomplete - in general, ask on the discussion page.
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* [[User:JSharp/Verax|Verax T2 Cluster System (w/ Coreboot-powered x86 Isolated Acceleration)]]
 
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* [[User:JSharp/Verus|Verus OpenPOWER POWER9 Portable Workstation]]
=== Primary Purpose ===
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* [[User:JSharp/oVRMc|oVRMc Open Source Multiphase PMBus/AVSBus POWER9-compatible Voltage Regulation Module Controller (open VRM controller)]]
Primary Purpose: (Heterogeneous Distributed OS Development)/(Data Processing)/(Firmware Integration and Development) and "General Purpose" Workstation System - Once mature to provide full-control/debugging environment for low-level systems testing and verification including hardware/bus interposers (digital/analogue capture) for qualified local/remote users.
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* [[User:JSharp/PowerLine|cycle/bus/transaction accurate simulation of the (POWER9/T2 SoC IPL) for FW development/verification]]
 
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** Design, Implementation and Verification of a cycle/bus accurate simulation of the POWER9/T2 IPL for use in systems firmware development and verification.  I haven't been able to find an existing method for fully simulating systems firmware deployment and execution not involving actual hardware and support infrastructure. Ideally, physical hardware would be used only for model verification. More research on exist methods of development required.
=== Components ===
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* [[User:JSharp/Durania|formally verified re-implementation of OpenPOWER equivalent P9 SoC firmware]]
 
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** Formal verification of low-level systems firmware is vital for stability, security and algorithm correctness. Do so via re-implementation of OpenPOWER provided firmware equivalent POWER9 SoC firmware specifications/build systems using Ivory/Tower eDSL Models enhanced with LiquidHaskell refinement type system. Use Simulation to validate equivalent initialisation and run-time behaviour versus OpenPOWER provided firmwares.
Incomplete list, acquisition status to be added (though the majority of components have been acquired).
 
 
 
* Infrastructure
 
** 1x CyberPower CR24U11001 24U Rack Enclosure
 
** 3x TCG TGC-H4-650 Chassis 4U 650mm Depth w/o PSU
 
** 1x Thermaltake Core W200 Chassis (Dual System, 1x RCS T2/1x x86)
 
* Power Routing and Management
 
** 2x APC SMX3000HV Smart-UPS 3000VA (4U)
 
** 2x CyberPower PDU20MHVIEC10AT Metered Auto-transfer Switch (1U)
 
* Power Conversion
 
** 5x Corsair AX1500i Power Supply
 
* Data Routing/Transfer
 
** 1x Arista DCS-7050QX-32 (QSFP+) (1U)
 
** 1x Cisco SG-500X-24-K9 (1U)
 
** 10x Mellanox MCX314A-BCBT ConnectX-3 Ethernet Adapters (Dual Port)
 
* Data Storage Elements
 
** 30x Seagate BarraCuda ST8000DM004 8TB SATA HDDs (coldline)
 
** 10x Samsung EVO PRO 860 1TB SATA SSDs (warmline)
 
** 5x LSI 9300-8i SATA/SAS HBA
 
** 8x Intel 900P (4x PCI Express/4x OCuLink) NVMe 480GB (hotline)
 
** 32x Samsung M393A2G40EB2 16GB DDR4-2667 ECC DRAM (online - POWER) (64x once tested)
 
** 8x Micron MT36KSF2G72PZ-1G6E1FE 16GB DDR3-1600 ECC DRAM (online - x86) (16x once memory controller patched, known coreboot issues)
 
* Data Processing Elements/Backplane
 
** 4x Raptor Computing Systems T2P9D01 Talos II Mainboard
 
** 1x ASUS KGPE-D16 Mainboard
 
** 2x AMD Opteron 6378 CPU
 
** 8x IBM POWER9 CPU (18-Core)
 
** 6x AMD Radeon Pro WX 7100
 
 
 
=== Sub-Projects (in order of interest/work likelyhood) ===
 
 
 
==== cycle/bus accurate simulation of the (POWER9/T2 SoC IPL) for FW development/verification ====
 
 
 
Design, Implementation and Verification of a cycle/bus accurate simulation of the POWER9/T2 IPL for use in systems firmware development and verification.  I haven't been able to find an existing method for fully simulating systems firmware deployment and execution not involving actual hardware and support infrastructure. Ideally, physical hardware would be used only for model verification. More research on exist methods of development required.
 

Latest revision as of 03:40, 20 November 2018

Hi There. I'm a Systems Engineer and Hobbyist.

My other social media accounts

  • twitter.com/justinrwlynn

.plan

  • Mine/Review [1] for additional documentation
  • Also Mine/Review [2]

Projects (in order of interest/work likelihood)