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Revision as of 23:03, 19 September 2022 by JeremyRand (talk | contribs) (Link to datasheet)
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Package Information
Processor POWER8
Structure SCM
Maximum base clock -
Maximum turbo clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 3
Maximum PCIe lanes 40
Maximum PCIe endpoints 3
CAPI interfaces 2


Sourced from POWER8 data sheet v2.4 (see Table 6-2 on page 63).