Difference between revisions of "Sforza"

From RCS Wiki
Jump to navigation Jump to search
(→‎Configurations: replacing from datasheet)
Line 145: Line 145:
 
| 02AA986
 
| 02AA986
 
| 16
 
| 16
|  
+
| DD2.1
| 2.9/3.8
+
| 1.600/3.80/2.90
 
| 190 W
 
| 190 W
 +
|-
 +
| 02CY977
 +
|rowspan=2| 8
 +
| DD2.2
 +
|rowspan=2| 1.867/4.10/3.80
 +
|rowspan=2| 190 W
 +
|-
 +
| 02WP000
 +
| DD2.3
 
|-
 
|-
 
| 02CY414
 
| 02CY414
| 22
+
|rowspan=2| 22
|  
+
| DD2.2
| 2.25/3.8
+
|rowspan=2| 1.867/3.80/2.25
| 160 W
+
|rowspan=2| 160 W
 +
|-
 +
| 02CY644
 +
| DD2.3
 
|-
 
|-
 
| 02CY415
 
| 02CY415
| 20
+
|rowspan=2| 20
|  
+
| DD2.2
| 2.4/3.8
+
|rowspan=2| 1.867/3.80/2.40
 +
|rowspan=2| 160 W
 +
|-
 +
| 02CY645
 +
| DD2.3
 +
|-
 +
| 02CY231
 +
|rowspan=2| 16
 +
| DD2.2
 +
|rowspan=2| 1.867/3.80/2.50
 +
|rowspan=2| 160 W
 +
|-
 +
| 02CY641
 +
| DD2.3
 +
|-
 +
| 02AA882
 +
| 16
 +
| DD2.1
 +
| 1.600/3.40/2.20
 
| 160 W
 
| 160 W
 
|-
 
|-
 
| 02CY416
 
| 02CY416
| 18
+
|rowspan=2| 18
 +
| DD2.2
 +
|rowspan=2| 1.867/3.80/2.25
 +
|rowspan=2| 130 W
 +
|-
 +
| 02CY647
 +
| DD2.3
 +
|-
 +
| 02CY417
 +
|rowspan=2| 16
 
|  
 
|  
| 2.25/3.8
+
|rowspan=2| 2.3/3.8
| 130 W
+
|rowspan=2| 130 W
 
|-
 
|-
| 02CY417
 
| 16
 
 
|  
 
|  
| 2.3/3.8
+
|  
| 130 W
 
 
|- <!-- WikiChip and https://twitter.com/SamatJain/status/1246199602144927744 -->
 
|- <!-- WikiChip and https://twitter.com/SamatJain/status/1246199602144927744 -->
 
| 02CY771
 
| 02CY771

Revision as of 21:06, 2 May 2020

Package Information
Sforza
Processor POWER9
Chip Nimbus
Maximum base clock 3.1GHz (4/8 core)
Maximum WOF clock 3.8GHz (4/8 core)
Maximum TDP 190W
PCIe controllers (PEC) 3
PCIe generation 4
Maximum PCIe lanes 48
Maximum PCIe endpoints 6
CAPI 2.0 interfaces 2
OpenCAPI interfaces 0
NVLink interfaces 0

For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see Nimbus.

Sforza is the codename for a POWER9, Nimbus chip, CPU module/package designed for general purpose computing, with high I/O available over standard PCIe generation 4 interfaces. The Nimbus chip it houses has 24 cores on the die, each capable of SMT4, and as a Scale Out processor intended for dual socket systems, uses directly attached RAM.

It is used by the Talos™ II systems.

Configurations

As with many CPUs, Nimbus-Sforza modules can be sold with some number of CPU cores disabled, and with different default clock speeds; at this time, no known Nimbus-Sforza parts are available with all 24 cores enabled.

Parts sold by RCS
Part SKU Name Cores Stepping TDP
02CY297 CP9M01 IBM POWER9 CPU (4-Core) 4 DD2.2 90 W
02CY089 CP9M02 IBM POWER9 CPU (8-Core) 8 DD2.2 160 W
02CY489 CP9M06 IBM POWER9 CPU (18-Core) 18 DD2.2 190 W
02CY296? CP9M08 IBM POWER9 CPU (22-Core) 22 DD2.2 190 W
CP9M31 IBM POWER9 v2 CPU (4-Core) 4 DD2.3 90 W
02CY649 CP9M32 IBM POWER9 v2 CPU (8-Core) 8 DD2.3 160 W
Other known Sforza parts
Part Cores Stepping Nest/Boost/Base (GHz) Max
02CY296 22 DD2.2 1.867/3.80/2.75 190 W
02CY642 DD2.3
02CY227 22 DD2.2 1.867/3.80/2.60 190 W
02CY639 DD2.3
02CY228 20 DD2.2 1.867/3.80/2.70 190 W
02CY637 DD2.3
02CY489 18 DD2.2 1.867/3.80/2.80 190 W
02CY646 DD2.3
02CY230 16 DD2.2 1.867/3.80/2.90 190 W
02CY640 DD2.3
02AA986 16 DD2.1 1.600/3.80/2.90 190 W
02CY977 8 DD2.2 1.867/4.10/3.80 190 W
02WP000 DD2.3
02CY414 22 DD2.2 1.867/3.80/2.25 160 W
02CY644 DD2.3
02CY415 20 DD2.2 1.867/3.80/2.40 160 W
02CY645 DD2.3
02CY231 16 DD2.2 1.867/3.80/2.50 160 W
02CY641 DD2.3
02AA882 16 DD2.1 1.600/3.40/2.20 160 W
02CY416 18 DD2.2 1.867/3.80/2.25 130 W
02CY647 DD2.3
02CY417 16 2.3/3.8 130 W
02CY771 12 2.2/3.8 105 W

Partly sourced from Sforza datasheet (see Table 6-1 on page 59 in version 1.8)

External Links